Using two ADI' s AD9226, this chip is a single chip, 12, 65 MSPS ADC (ADC), a single power supply, which speeds up data 65 MSPS. The data based on fpga using verilog language programming.

ALINX9226_406
.............\AD.bsf
.............\AD.v
.............\AD.v.bak
.............\AD1.v
.............\AD1.v.bak
.............\ADDA.asm.rpt
.............\ADDA.bdf
.............\ADDA.done
.............\ADDA.fit.rpt
.............\ADDA.fit.smsg
.............\ADDA.fit.summary
.............\ADDA.flow.rpt
.............\ADDA.jdi
.............\ADDA.map.rpt
.............\ADDA.map.summary
.............\ADDA.merge.rpt
.............\ADDA.pin
.............\ADDA.pof
.............\ADDA.qpf
.............\ADDA.qsf
.............\ADDA.restore.rpt
.............\ADDA.sof
.............\ADDA.sta.rpt
.............\ADDA.sta.summary
.............\ADDA.tcl
.............\ADDA.tcl.bak
.............\ADDA_assignment_defaults.qdf
.............\cpu1.sdc
.............\cpu2.sdc
.............\DA.v
.............\db
.............\..\ADDA.amm.cdb
.............\..\ADDA.asm.qmsg
.............\..\ADDA.asm.rdb
.............\..\ADDA.asm_labs.ddb
.............\..\ADDA.cbx.xml
.............\..\ADDA.cmp.bpm
.............\..\ADDA.cmp.cdb
.............\..\ADDA.cmp.hdb
.............\..\ADDA.cmp.kpt
.............\..\ADDA.cmp.logdb
.............\..\ADDA.cmp.rdb
.............\..\ADDA.cmp_merge.kpt
.............\..\ADDA.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
.............\..\ADDA.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
.............\..\ADDA.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
.............\..\ADDA.db_info
.............\..\ADDA.fit.qmsg
.............\..\ADDA.hier_info
.............\..\ADDA.hif
.............\..\ADDA.idb.cdb
.............\..\ADDA.lpc.html
.............\..\ADDA.lpc.rdb
.............\..\ADDA.lpc.txt
.............\..\ADDA.map.bpm
.............\..\ADDA.map.cdb
.............\..\ADDA.map.hdb
.............\..\ADDA.map.kpt
.............\..\ADDA.map.logdb
.............\..\ADDA.map.qmsg
.............\..\ADDA.map_bb.cdb
.............\..\ADDA.map_bb.hdb
.............\..\ADDA.map_bb.logdb
.............\..\ADDA.pre_map.cdb
.............\..\ADDA.pre_map.hdb
.............\..\ADDA.rtlv.hdb
.............\..\ADDA.rtlv_sg.cdb
.............\..\ADDA.rtlv_sg_swap.cdb
.............\..\ADDA.sgdiff.cdb
.............\..\ADDA.sgdiff.hdb
.............\..\ADDA.sld_design_entry.sci
.............\..\ADDA.sld_design_entry_dsc.sci
.............\..\ADDA.smart_action.txt
.............\..\ADDA.sta.qmsg
.............\..\ADDA.sta.rdb
.............\..\ADDA.sta_cmp.8_slow_1200mv_85c.tdb
.............\..\ADDA.syn_hier_info
.............\..\ADDA.tiscmp.fastest_slow_1200mv_0c.ddb
.............\..\ADDA.tiscmp.fastest_slow_1200mv_85c.ddb
.............\..\ADDA.tiscmp.fast_1200mv_0c.ddb
.............\..\ADDA.tiscmp.slow_1200mv_0c.ddb
.............\..\ADDA.tiscmp.slow_1200mv_85c.ddb
.............\..\ADDA.tis_db_list.ddb
.............\..\altsyncram_0124.tdf
.............\..\altsyncram_2124.tdf
.............\..\altsyncram_e124.tdf
.............\..\altsyncram_s024.tdf
.............\..\cmpr_ngc.tdf
.............\..\cmpr_qgc.tdf
.............\..\cmpr_rgc.tdf
.............\..\cmpr_sgc.tdf
.............\..\cntr_23j.tdf
.............\..\cntr_bgi.tdf
.............\..\cntr_egi.tdf
.............\..\cntr_fgi.tdf
.............\..\cntr_g9j.tdf
.............\..\cntr_igi.tdf
.............\..\cntr_mgi.tdf
.............\..\cntr_o9j.tdf

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