This a sample microprocessor with a bi-directional data bus and RAM in software created in VHDL run on a cyclone 3 FPGA.

Lab7
....\adder.vhd
....\ALU.vhd
....\ALU_tb.vhd
....\controller.vhd
....\datapath.vhd
....\datapath2_tb.vhd
....\datapath3_tb.vhd
....\datapath_mult_6b_tb.vhd
....\datapath_mult_tb.vhd
....\datapath_tb.vhd
....\datapath_tc1_tb.vhd
....\db
....\..\altsyncram_4f14.tdf
....\..\altsyncram_8ek1.tdf
....\..\altsyncram_9ek1.tdf
....\..\altsyncram_aek1.tdf
....\..\altsyncram_asj1.tdf
....\..\altsyncram_sjj1.tdf
....\..\altsyncram_tvj1.tdf
....\..\decode_37a.tdf
....\..\decode_ara.tdf
....\..\logic_util_heursitic.dat
....\..\mult_19t.tdf
....\..\mux_qlb.tdf
....\..\prev_cmp_top_level.asm.qmsg
....\..\prev_cmp_top_level.eda.qmsg
....\..\prev_cmp_top_level.fit.qmsg
....\..\prev_cmp_top_level.map.qmsg
....\..\prev_cmp_top_level.qmsg
....\..\prev_cmp_top_level.sta.qmsg
....\..\top_level.asm.qmsg
....\..\top_level.asm.rdb
....\..\top_level.cbx.xml
....\..\top_level.cmp.bpm
....\..\top_level.cmp.cbp
....\..\top_level.cmp.ecobp
....\..\top_level.cmp.hdb
....\..\top_level.cmp.kpt
....\..\top_level.cmp_merge.kpt
....\..\top_level.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
....\..\top_level.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
....\..\top_level.db_info
....\..\top_level.eco.cdb
....\..\top_level.eda.qmsg
....\..\top_level.fit.qmsg
....\..\top_level.hier_info
....\..\top_level.hif
....\..\top_level.lpc.html
....\..\top_level.lpc.rdb
....\..\top_level.lpc.txt
....\..\top_level.map.ecobp
....\..\top_level.map.kpt
....\..\top_level.map.qmsg
....\..\top_level.map_bb.cdb
....\..\top_level.map_bb.hdb
....\..\top_level.map_bb.logdb
....\..\top_level.pre_map.cdb
....\..\top_level.pre_map.hdb
....\..\top_level.rtlv.hdb
....\..\top_level.rtlv_sg.cdb
....\..\top_level.rtlv_sg_swap.cdb
....\..\top_level.sgdiff.cdb
....\..\top_level.sgdiff.hdb
....\..\top_level.sld_design_entry.sci
....\..\top_level.sld_design_entry_dsc.sci
....\..\top_level.smart_action.txt
....\..\top_level.smp_dump.txt
....\..\top_level.sta.qmsg
....\..\top_level.syn_hier_info
....\..\top_level.tiscmp.slow_1200mv_85c.ddb
....\decoder.vhd
....\decoder7seg.vhd
....\external_db.vhd
....\incremental_db
....\..............\compiled_partitions
....\..............\...................\top_level.root_partition.cmp.cdb
....\..............\...................\top_level.root_partition.cmp.dfp
....\..............\...................\top_level.root_partition.cmp.hdb
....\..............\...................\top_level.root_partition.cmp.kpt
....\..............\...................\top_level.root_partition.cmp.logdb
....\..............\...................\top_level.root_partition.cmp.rcfdb
....\..............\...................\top_level.root_partition.cmp.re.rcfdb
....\..............\...................\top_level.root_partition.map.cdb
....\..............\...................\top_level.root_partition.map.dpi
....\..............\...................\top_level.root_partition.map.hdb
....\..............\...................\top_level.root_partition.map.kpt
....\..............\README
....\internal_db.vhd
....\IO_ports.vhd
....\Lab7_d2.ipinfo
....\Lab7_d4.ipinfo
....\Lab7_d4_tc3.ipinfo
....\Lab7_d6a.ipinfo
....\multiplier.vhd
....\mult_6b_memory.cmp
....\mult_6b_memory.qip
....\mult_6b_memory.vhd
....\mult_6b_memory_wave0.jpg
....\mult_6b_memory_waveforms.html

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