The SAYEH (Simple Architecture, Yet Enough Hardware) is a processor architecture that has been developed by Navabi in [1] for experimental and teaching purposes. As the name implies it is a “simple” architecture but contains sufficient hardware to make it a challenge. In this and the following workshops we will be developing this processor architecture to practice our skills in developing VHDL code which will be useful in later laboratories when we will be building more complex structures. Unfortunately the SAYEH code provided by Navabi is written in Verilog, we will be translating it to VHDL.

SAYEN
.....\AddressLogic.vhd
.....\AddressLogic.vhd.bak
.....\ALUx.VHD
.....\ALUx.VHD.bak
.....\InstructionFSM.vhd
.....\Instruction_Register.VHD
.....\Instruction_Register.VHD.bak
.....\progmem.vhd
.....\ProgrammCounter.vhd
.....\ProgrammCounter.vhd.bak
.....\RegFile.vhd
.....\RegisterFile.vhd
.....\RegisterFile.vhd.bak
.....\sayeh.coe
.....\SAYEH_TOP.vhd
.....\SAYEH_TOP.vhd.bak
.....\Status_Register.vhd
.....\Status_Register.vhd.bak
.....\WindowPointer.vhd
.....\WindowPointer.vhd.bak
SAYEN_TB
........\AddressLogic_TB.vhd
........\AddressLogic_TB.vhd.bak
........\ALUx_TB.vhd
........\ALUx_TB.vhd.bak
........\InstructionFSM_TB.vhd
........\InstructionRegister_TB.vhd
........\InstructionRegister_TB.vhd.bak
........\progmem_TB.vhd
........\ProgramCounter_TB.vhd
........\ProgramCounter_TB.vhd.bak
........\RegFile_TB.vhd
........\SAYEH_PROG_TB.vhd
........\SAYEH_TOP_TB.vhd
........\SAYEH_TOP_TB.vhd.bak
........\WindowPointer_TB.vhd
........\WindowPointer_TB.vhd.bak

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