The FPGA development instance of the design with VHDL voter of seven people

Example18\db\exp18.asm.qmsg
.........\..\exp18.asm_labs.ddb
.........\..\exp18.cbx.xml
.........\..\exp18.cmp.bpm
.........\..\exp18.cmp.cdb
.........\..\exp18.cmp.ecobp
.........\..\exp18.cmp.hdb
.........\..\exp18.cmp.kpt
.........\..\exp18.cmp.logdb
.........\..\exp18.cmp.rdb
.........\..\exp18.cmp_merge.kpt
.........\..\exp18.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
.........\..\exp18.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
.........\..\exp18.db_info
.........\..\exp18.eco.cdb
.........\..\exp18.eda.qmsg
.........\..\exp18.fit.qmsg
.........\..\exp18.hier_info
.........\..\exp18.hif
.........\..\exp18.map.bpm
.........\..\exp18.map.cdb
.........\..\exp18.map.ecobp
.........\..\exp18.map.hdb
.........\..\exp18.map.kpt
.........\..\exp18.map.logdb
.........\..\exp18.map.qmsg
.........\..\exp18.map_bb.cdb
.........\..\exp18.map_bb.hdb
.........\..\exp18.map_bb.hdbx
.........\..\exp18.map_bb.logdb
.........\..\exp18.pre_map.cdb
.........\..\exp18.pre_map.hdb
.........\..\exp18.psp
.........\..\exp18.rtlv.hdb
.........\..\exp18.rtlv_sg.cdb
.........\..\exp18.rtlv_sg_swap.cdb
.........\..\exp18.sgdiff.cdb
.........\..\exp18.sgdiff.hdb
.........\..\exp18.sld_design_entry.sci
.........\..\exp18.sld_design_entry_dsc.sci
.........\..\exp18.sta.qmsg
.........\..\exp18.sta.rdb
.........\..\exp18.sta_cmp.8_slow_1200mv_85c.tdb
.........\..\exp18.syn_hier_info
.........\..\exp18.tiscmp.fastest_slow_1200mv_0c.ddb
.........\..\exp18.tiscmp.fastest_slow_1200mv_85c.ddb
.........\..\exp18.tiscmp.fast_1200mv_0c.ddb
.........\..\exp18.tiscmp.slow_1200mv_0c.ddb
.........\..\exp18.tiscmp.slow_1200mv_85c.ddb
.........\..\exp18.tis_db_list.ddb
.........\..\exp18.tmw_info
.........\..\prev_cmp_exp18.asm.qmsg
.........\..\prev_cmp_exp18.eda.qmsg
.........\..\prev_cmp_exp18.fit.qmsg
.........\..\prev_cmp_exp18.map.qmsg
.........\..\prev_cmp_exp18.qmsg
.........\..\prev_cmp_exp18.sta.qmsg
.........\exp18.asm.rpt
.........\exp18.done
.........\exp18.eda.rpt
.........\exp18.fit.rpt
.........\exp18.fit.smsg
.........\exp18.fit.summary
.........\exp18.flow.rpt
.........\exp18.map.rpt
.........\exp18.map.summary
.........\exp18.pin
.........\exp18.qpf
.........\exp18.qsf
.........\exp18.qws
.........\exp18.sof
.........\exp18.sta.rpt
.........\exp18.sta.summary
.........\exp18.vhd
.........\exp18.vhd.bak
.........\incremental_db\compiled_partitions\exp18.root_partition.cmp.atm
.........\..............\...................\exp18.root_partition.cmp.dfp
.........\..............\...................\exp18.root_partition.cmp.hdbx
.........\..............\...................\exp18.root_partition.cmp.kpt
.........\..............\...................\exp18.root_partition.cmp.logdb
.........\..............\...................\exp18.root_partition.cmp.rcf
.........\..............\...................\exp18.root_partition.map.atm
.........\..............\...................\exp18.root_partition.map.dpi
.........\..............\...................\exp18.root_partition.map.hdbx
.........\..............\...................\exp18.root_partition.map.kpt
.........\..............\README
.........\simulation\modelsim\exp18.sft
.........\..........\........\exp18.vho
.........\..........\........\exp18_8_1200mv_0c_vhd_slow.sdo
.........\..........\........\exp18_8_1200mv_85c_vhd_slow.sdo
.........\..........\........\exp18_min_1200mv_0c_vhd_fast.sdo
.........\..........\........\exp18_modelsim.xrf
.........\..........\........\exp18_vhd.sdo
.........\timing\primetime\exp18.collections.sdc
.........\......\.........\exp18.constraints.sdc
.........\......\.........\exp18.pt.tcl
.........\......\.........\exp18.vo
.........\......\.........\exp18_8_1200mv_0c_v_slow.sdo
.........\......\.........\exp18_8_1200mv_85c_v_slow.sdo
.........\......\.........\exp18_min_1200mv_0c_v_fast.sdo

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