256*8 memory, using Verilog language

ram256x8\db\altsyncram_1h71.tdf
........\..\prev_cmp_ram256x8.map.qmsg
........\..\ram256x8.cbx.xml
........\..\ram256x8.cmp.rdb
........\..\ram256x8.dbp
........\..\ram256x8.db_info
........\..\ram256x8.eco.cdb
........\..\ram256x8.hier_info
........\..\ram256x8.hif
........\..\ram256x8.map.bpm
........\..\ram256x8.map.cdb
........\..\ram256x8.map.ecobp
........\..\ram256x8.map.hdb
........\..\ram256x8.map.logdb
........\..\ram256x8.map.qmsg
........\..\ram256x8.map_bb.cdb
........\..\ram256x8.map_bb.hdb
........\..\ram256x8.map_bb.logdb
........\..\ram256x8.pre_map.cdb
........\..\ram256x8.pre_map.hdb
........\..\ram256x8.psp
........\..\ram256x8.pss
........\..\ram256x8.rpp.qmsg
........\..\ram256x8.rtlv.hdb
........\..\ram256x8.rtlv_sg.cdb
........\..\ram256x8.rtlv_sg_swap.cdb
........\..\ram256x8.sgate.rvd
........\..\ram256x8.sgate_sm.rvd
........\..\ram256x8.sgdiff.cdb
........\..\ram256x8.sgdiff.hdb
........\..\ram256x8.sld_design_entry.sci
........\..\ram256x8.sld_design_entry_dsc.sci
........\..\ram256x8.syn_hier_info
........\..\ram256x8.tis_db_list.ddb
........\ram256x8.done
........\ram256x8.flow.rpt
........\ram256x8.map.rpt
........\ram256x8.map.summary
........\ram256x8.qpf
........\ram256x8.qsf
........\ram256x8.qsf.bak
........\ram256x8.qws
........\RTL\ram256x8.v
........\...\ram256x8.v.bak
........\db
........\RTL
ram256x8

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