A 331 procedures implemented by verilog, used in fpga, connect the monitor, you can choose to play against the computer or a double play, press wsad control the direction, carriage control Lazi, the program will automatically determine the winners and losers and display the results

vga\.lso
...\clk_driver.v
...\clk_driver.v.bak
...\fuzhiyong.v
...\fz.v
...\haishifuzhiyong.v
...\judge_win.v
...\judge_win.v.bak
...\ps2_ctlr.v
...\ps2_ctlr_summary.html
...\ps2_kbd_driver.v
...\qipan_show.prj
...\qipan_show.stx
...\qipan_show.v
...\qipan_show.v.bak
...\qipan_show.xst
...\qipan_show_vhdl.prj
...\testbench.cmd_log
...\testbench.lso
...\testbench.prj
...\testbench.syr
...\testbench.v
...\testbench.v.bak
...\testbench.xst
...\testbench_summary.html
...\testbench_vhdl.prj
...\top.bgn
...\top.bit
...\top.bld
...\top.cel
...\top.cmd_log
...\top.drc
...\top.lso
...\top.ncd
...\top.ngc
...\top.ngd
...\top.ngr
...\top.pad
...\top.par
...\top.pcf
...\top.prj
...\top.stx
...\top.syr
...\top.twr
...\top.twx
...\top.ucf
...\top.unroutes
...\top.ut
...\top.v
...\top.v.bak
...\top.xpi
...\top.xst
...\top_chess.v
...\top_chess.v.bak
...\top_last_par.ncd
...\top_light.v
...\top_luozi.v
...\top_luozi.v.bak
...\top_map.mrp
...\top_map.ncd
...\top_map.ngm
...\top_pad.csv
...\top_pad.txt
...\top_prev_built.ngd
...\top_pve.v
...\top_pve.v.bak
...\top_renji.v
...\top_summary.html
...\top_usage.xml
...\top_vhdl.prj
...\transcript
...\vga.ise
...\vga.ise_ISE_Backup
...\vga.ntrc_log
...\VGA_crl.prj
...\VGA_crl.spl
...\VGA_crl.stx
...\VGA_crl.sym
...\vga_crl.v
...\VGA_crl.xst
...\VGA_crl_vhdl.prj
...\xst\dump.xst\testbench.prj\ntrc.scr
...\...\........\.op.prj\ntrc.scr
...\...\work\hdllib.ref
...\...\....\vlg01\top__luozi.bin
...\...\....\....3\judge__win__mol.bin
...\...\....\....5\top__pve.bin
...\...\....\....E\top__light.bin
...\...\....\...1C\top__chess.bin
...\...\....\....D\qipan__show.bin
...\...\....\....E\_v_g_a__crl.bin
...\...\....\...24\ps2__kbd__driver.bin
...\...\....\...39\choose__show.bin
...\...\....\....D\ps2__ctlr.bin
...\...\....\...47\clk__diver.bin
...\...\....\...6C\testbench.bin
...\...\....\....E\top__renji.bin
...\...\....\....F\top.bin
...\...\....\...7E\vga__crl.bin
...\zhantieyong.v

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