Written by verilog simple class multi-cycle pipelined MIPS processor, the basic features include 9 instruction and two dynamic branch prediction, compressed bag word specifies the details of the structure

计算机组成实验报告.docx
modelsim仿真代码\binary.txt
................\branchtb.txt
................\branch_table.v
................\DATA2.txt
................\EX.v
................\ID.v
................\ID.v.bak
................\IF.v
................\MEM.v
................\mips.v
................\mips_constant.v
................\mips_tb.v
................\reg_file.v
................\reg_stage.v
................\WB.v
modelsim仿真代码

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