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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-04-06
  • Size : 6kb
  • Downloaded :0次
  • Author :刘***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Design a program with Verilog have time, calibration, alarm clock, calendar and other functions of electronic clock
Packet file list
(Preview for download)


程序清单\分频模块.txt
........\按键去抖动模块.txt
........\数码管显示模块.txt
........\日历模块.txt
........\日期校准模块.txt
........\时钟校准模块.txt
........\时间模块.txt
........\译码模块.txt
........\选择显示功能模块.txt
........\闹钟模块.txt
........\闹钟设置模块.txt
程序清单
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