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rtl_viterbi_veeRen

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-04-07
  • Size : 6kb
  • Downloaded :0次
  • Author :h***
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Introduction - If you have any usage issues, please Google them yourself
RTL design Viterbi decoder using VHDL
Packet file list
(Preview for download)


rtl_viterbi\ACSblock2.vhd
...........\ACS_Top.vhd
...........\BranchMetric.vhd
...........\ConvEnc.vhd
...........\MinState.vhd
...........\pathchange.vhd
...........\random_binary.vhd
...........\selectpath.vhd
...........\test_constant.vhd
...........\top_ConvEnc.vhd
...........\viterbi_top.vhd
rtl_viterbi
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