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traffic_ligt_controller_veeren

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2015-04-13
  • Size : 35kb
  • Downloaded :0次
  • Author :h***
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traffic light controller
Packet file list
(Preview for download)


traffic_controller\bench\tb_traffic_controller.v
..................\rtl\cnter_enb_ovf.v
..................\...\traffic_controller.v
..................\...\traffic_sm.v
..................\sim\History
..................\...\traffic_controller.cr.mti
..................\...\traffic_controller.mpf
..................\...\vsim.wlf
..................\...\wave.do
..................\...\.ork\cnter_enb_ovf\verilog.asm
..................\...\....\.............\_primary.dat
..................\...\....\.............\_primary.vhd
..................\...\....\tb_traffic_controller\fast.asm
..................\...\....\.....................\verilog.asm
..................\...\....\.....................\_primary.dat
..................\...\....\.....................\_primary.vhd
..................\...\....\.raffic_controller\verilog.asm
..................\...\....\..................\_primary.dat
..................\...\....\..................\_primary.vhd
..................\...\....\........sm\verilog.asm
..................\...\....\..........\_primary.dat
..................\...\....\..........\_primary.vhd
..................\...\....\_info
..................\...\....\cnter_enb_ovf
..................\...\....\tb_traffic_controller
..................\...\....\traffic_controller
..................\...\....\traffic_sm
..................\...\work
..................\bench
..................\doc
..................\rtl
..................\sim
traffic_controller
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