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  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-04-13
  • Size : 8.13mb
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  • Author :Ser***
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VGA project for DE0-nano
Packet file list
(Preview for download)


vga
...\DE0_User_manual_2012.pdf
...\FPGA_VGA
...\FPGA_VGA.zip
...\........\.sopc_builder
...\........\.............\filters.xml
...\........\.............\install.ptf
...\........\.............\install2.ptf
...\........\.............\preferences.xml
...\........\PLLJ_PLLSPE_INFO.txt
...\........\SDC1.sdc
...\........\SDC1.sdc.bak
...\........\clock_crossing_io.v
...\........\cpu.ocp
...\........\cpu.sdc
...\........\cpu.v
...\........\cpu_bht_ram.mif
...\........\cpu_dc_tag_ram.mif
...\........\cpu_ic_tag_ram.mif
...\........\cpu_jtag_debug_module_sysclk.v
...\........\cpu_jtag_debug_module_tck.v
...\........\cpu_jtag_debug_module_wrapper.v
...\........\cpu_mult_cell.v
...\........\cpu_oci_test_bench.v
...\........\cpu_ociram_default_contents.mif
...\........\cpu_rf_ram_a.mif
...\........\cpu_rf_ram_b.mif
...\........\cpu_test_bench.v
...\........\data_format_adapter.v
...\........\data_format_adapter.vo
...\........\empty1.asm.rpt
...\........\empty1.bdf
...\........\empty1.done
...\........\empty1.fit.rpt
...\........\empty1.fit.smsg
...\........\empty1.fit.summary
...\........\empty1.flow.rpt
...\........\empty1.jdi
...\........\empty1.map.rpt
...\........\empty1.map.smsg
...\........\empty1.map.summary
...\........\empty1.pin
...\........\empty1.qpf
...\........\empty1.qsf
...\........\empty1.sof
...\........\empty1.sta.rpt
...\........\empty1.sta.summary
...\........\jtag_uart.v
...\........\lcd_64_to_8_bits_dfa.v
...\........\lcd_64_to_8_bits_dfa.vo
...\........\lcd_64_to_8_bits_dfa_data_ram.v
...\........\lcd_64_to_8_bits_dfa_state_ram.v
...\........\lcd_pixel_fifo.v
...\........\lcd_sgdma.v
...\........\lcd_ta_fifo_to_dfa.v
...\........\lcd_ta_fifo_to_dfa.vo
...\........\lcd_ta_fifo_to_dfa_fifo.v
...\........\lcd_ta_sgdma_to_fifo.v
...\........\lcd_ta_sgdma_to_fifo.vo
...\........\led_pio.v
...\........\nios_simple.bsf
...\........\nios_simple.html
...\........\nios_simple.ptf
...\........\nios_simple.ptf.8.0
...\........\nios_simple.ptf.bak
...\........\nios_simple.ptf.pre_generation_ptf
...\........\nios_simple.qip
...\........\nios_simple.sopc
...\........\nios_simple.sopcinfo
...\........\nios_simple.v
...\........\nios_simple_clock_0.v
...\........\nios_simple_generation_script
...\........\nios_simple_inst.v
...\........\nios_simple_log.txt
...\........\nios_simple_sim
...\........\...............\atail-f.pl
...\........\...............\jtag_uart_input_mutex.dat
...\........\...............\jtag_uart_input_stream.dat
...\........\...............\jtag_uart_output_stream.dat
...\........\pll.v
...\........\pll.vo
...\........\sdram.v
...\........\sdram_test_component.v
...\........\simgen_temp
...\........\...........\data_format_adapter.qpf
...\........\...........\data_format_adapter.qsf
...\........\...........\data_format_adapter.v
...\........\...........\data_format_adapter.vo
...\........\...........\data_format_adapter_simgen_gate.xml
...\........\...........\db
...\........\...........\..\data_format_adapter.cbx.xml
...\........\...........\..\data_format_adapter.db_info
...\........\...........\..\data_format_adapter.hier_info
...\........\...........\..\data_format_adapter.lpc.html
...\........\...........\..\data_format_adapter.lpc.rdb
...\........\...........\..\data_format_adapter.lpc.txt
...\........\...........\..\data_format_adapter.map.qmsg
...\........\...........\..\data_format_adapter.pre_map.cdb
...\........\...........\..\data_format_adapter.pre_map.hdb
...\........\...........\..\data_format_adapter.sld_design_entry_dsc.sci
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