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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2015-04-14
  • Size : 1.35mb
  • Downloaded :0次
  • Author :R****
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Introduction - If you have any usage issues, please Google them yourself
design of cache to remove tag bits
Packet file list
(Preview for download)


xst\work\work.sdbl
...\....\work.sdbx
.prj
.stx
.xst
blockMux_256x1.v
byteMux_16x1.v
cache.lso
cache.prj
cache.stx
cache.v
cache.xst
cache_summary.html
cacheauxarray.v
cacheblock.v
cacheByte.v
cacheMux_2x1_4bit.v
cacheMux_4x1_8bit.v
cacheTag.v
cacheWay.v
Ch.gise
Ch.xise
comparator_11bit.v
decoder_2x4.v
decoder_4x16.v
decoder_8x256.v
decoder16.v
DFlipFlop.v
fifo_replacement.v
priorityEncoder_4x2.v
refBits.v
refMux_2x1_2bit.v
refMux_256x1_8bit.v
replacementWay.v
tagMux_256x1.v
upCounter_5bit.v
_xmsgs\pn_parser.xmsgs
......\xst.xmsgs
iseconfig\cache.xreport
.........\Ch.projectmgr
xst\projnav.tmp
...\work
xst
_xmsgs
ipcore_dir
iseconfig
cache.cmd_log
cache.ngr
cache.syr
cache_envsettings.html
cache_xst.xrpt
decoder16.lso
decoder16.prj
decoder16.stx
decoder16.xst
webtalk_pn.xml
xst\dump.xst\cache.prj
...\dump.xst
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