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my_example

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-04-17
  • Size : 2mb
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  • Author :天***
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Introduction - If you have any usage issues, please Google them yourself
Based on SOPC built CPU, LCD display with DE2-70 do with the c language written.
Packet file list
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my_example\.sopc_builder\filters.xml
..........\.............\install.ptf
..........\.............\install2.ptf
..........\.............\preferences.xml
..........\Chain1.cdf
..........\db\altsyncram_2b72.tdf
..........\..\altsyncram_9tl1.tdf
..........\..\altsyncram_e502.tdf
..........\..\altsyncram_nq22.tdf
..........\..\altsyncram_v5b1.tdf
..........\..\a_dpfifo_8t21.tdf
..........\..\a_fefifo_7cf.tdf
..........\..\cntr_fjb.tdf
..........\..\cntr_rj7.tdf
..........\..\decode_1oa.tdf
..........\..\dpram_5h21.tdf
..........\..\mux_ujb.tdf
..........\..\my_example.db_info
..........\..\my_example.sld_design_entry.sci
..........\..\prev_cmp_my_example.asm.qmsg
..........\..\prev_cmp_my_example.fit.qmsg
..........\..\prev_cmp_my_example.map.qmsg
..........\..\prev_cmp_my_example.qmsg
..........\..\prev_cmp_my_example.tan.qmsg
..........\..\scfifo_1n21.tdf
..........\incremental_db\compiled_partitions\my_example.db_info
..........\..............\...................\my_example.root_partition.cmp.atm
..........\..............\...................\my_example.root_partition.cmp.dfp
..........\..............\...................\my_example.root_partition.cmp.hdbx
..........\..............\...................\my_example.root_partition.cmp.kpt
..........\..............\...................\my_example.root_partition.cmp.logdb
..........\..............\...................\my_example.root_partition.cmp.rcf
..........\..............\...................\my_example.root_partition.map.atm
..........\..............\...................\my_example.root_partition.map.dpi
..........\..............\...................\my_example.root_partition.map.hdbx
..........\..............\...................\my_example.root_partition.map.kpt
..........\..............\...................\my_example.root_partition.merge_hb.atm
..........\..............\...................\my_example.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm
..........\..............\...................\my_example.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.dpi
..........\..............\...................\my_example.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.hdbx
..........\..............\...................\my_example.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.kpt
..........\..............\...................\my_example.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.logdb
..........\..............\README
..........\my_cpu.ocp
..........\my_cpu.sdc
..........\my_cpu.vhd
..........\my_cpu_jtag_debug_module_sysclk.vhd
..........\my_cpu_jtag_debug_module_tck.vhd
..........\my_cpu_jtag_debug_module_wrapper.vhd
..........\my_cpu_ociram_default_contents.mif
..........\my_cpu_oci_test_bench.vhd
..........\my_cpu_rf_ram.mif
..........\my_cpu_test_bench.vhd
..........\my_example.asm.rpt
..........\my_example.bdf
..........\my_example.done
..........\my_example.dpf
..........\my_example.fit.rpt
..........\my_example.fit.smsg
..........\my_example.fit.summary
..........\my_example.flow.rpt
..........\my_example.jdi
..........\my_example.map.rpt
..........\my_example.map.summary
..........\my_example.pin
..........\my_example.pof
..........\my_example.qpf
..........\my_example.qsf
..........\my_example.qws
..........\my_example.sof
..........\my_example.tan.rpt
..........\my_example.tan.summary
..........\my_example_assignment_defaults.qdf
..........\my_input1.vhd
..........\my_jtag.vhd
..........\my_lcd_BLON.vhd
..........\my_lcd_ctr_out.vhd
..........\my_lcd_data_out.vhd
..........\my_lcd_EN.vhd
..........\my_lcd_ON.vhd
..........\my_lcd_RS.vhd
..........\my_lcd_RW.vhd
..........\my_nios_cpu.bsf
..........\my_nios_cpu.html
..........\my_nios_cpu.ptf
..........\my_nios_cpu.ptf.8.0
..........\my_nios_cpu.ptf.bak
..........\my_nios_cpu.ptf.pre_generation_ptf
..........\my_nios_cpu.qip
..........\my_nios_cpu.sopc
..........\my_nios_cpu.sopcinfo
..........\my_nios_cpu.vhd
..........\my_nios_cpu_generation_script
..........\my_nios_cpu_inst.vhd
..........\my_nios_cpu_log.txt
..........\............sim\atail-f.pl
..........\...............\dummy_file
..........\...............\my_jtag_input_mutex.dat
....
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