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CRC32_D8

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-05-06
  • Size : 2.41mb
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  • Author :王***
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Introduction - If you have any usage issues, please Google them yourself
CRC coding, CRC32, verilog implementation, verification on xilinx platform, the results are available.
Packet file list
(Preview for download)


CRC32_D8
........\.Xil
........\....\Vivado-10876-zzzzzzzz-PC
........\CRC32_D8.cache
........\..............\compile_simlib
........\CRC32_D8.data
........\.............\constrs_1
........\.............\.........\designprops.xml
........\.............\.........\fileset.xml
........\.............\.........\usercols.xml
........\.............\runs
........\.............\....\impl_1
........\.............\....\......\constrs_in.xml
........\.............\....\......\impl_1.psg
........\.............\....\impl_1.psg
........\.............\....\runs.xml
........\.............\....\synth_1
........\.............\....\.......\constrs_in.xml
........\.............\....\.......\sources.xml
........\.............\....\.......\synth_1.psg
........\.............\....\synth_1.psg
........\.............\sim_1
........\.............\.....\fileset.xml
........\.............\sources_1
........\.............\.........\fileset.xml
........\.............\.........\ports.xml
........\.............\wt
........\.............\..\java_command_handlers.wdf
........\.............\..\project.wpc
........\.............\..\synthesis.wdf
........\.............\..\webtalk_pa.xml
........\.............\..\xsim.wdf
........\CRC32_D8.runs
........\.............\.jobs
........\.............\.....\vrs_config_1.xml
........\.............\.....\vrs_config_2.xml
........\.............\impl_1
........\.............\......\.Vivado Implementation.queue.rst
........\.............\......\.Xil
........\.............\......\.init_design.begin.rst
........\.............\......\.init_design.end.rst
........\.............\......\.opt_design.begin.rst
........\.............\......\.opt_design.end.rst
........\.............\......\.place_design.begin.rst
........\.............\......\.place_design.end.rst
........\.............\......\.route_design.begin.rst
........\.............\......\.route_design.end.rst
........\.............\......\.vivado.begin.rst
........\.............\......\.vivado.end.rst
........\.............\......\CRC32_D8.rdi
........\.............\......\CRC32_D8.tcl
........\.............\......\CRC32_D8_clock_utilization_placed.rpt
........\.............\......\CRC32_D8_control_sets_placed.rpt
........\.............\......\CRC32_D8_drc_routed.pb
........\.............\......\CRC32_D8_drc_routed.rpt
........\.............\......\CRC32_D8_io_placed.rpt
........\.............\......\CRC32_D8_opt.dcp
........\.............\......\CRC32_D8_placed.dcp
........\.............\......\CRC32_D8_power_routed.rpt
........\.............\......\CRC32_D8_power_summary_routed.pb
........\.............\......\CRC32_D8_route_status.pb
........\.............\......\CRC32_D8_route_status.rpt
........\.............\......\CRC32_D8_routed.dcp
........\.............\......\CRC32_D8_timing_summary_routed.pb
........\.............\......\CRC32_D8_timing_summary_routed.rpt
........\.............\......\CRC32_D8_utilization_placed.pb
........\.............\......\CRC32_D8_utilization_placed.rpt
........\.............\......\ISEWrap.js
........\.............\......\ISEWrap.sh
........\.............\......\htr.txt
........\.............\......\init_design.pb
........\.............\......\opt_design.pb
........\.............\......\place_design.pb
........\.............\......\project.wdf
........\.............\......\route_design.pb
........\.............\......\rundef.js
........\.............\......\runme.bat
........\.............\......\runme.log
........\.............\......\runme.sh
........\.............\......\vivado.jou
........\.............\......\vivado.pb
........\.............\synth_1
........\.............\.......\.Vivado Synthesis.queue.rst
........\.............\.......\.Xil
........\.............\.......\....\CRC32_D8_propImpl.xdc
........\.............\.......\.vivado.begin.rst
........\.............\.......\.vivado.end.rst
........\.............\.......\CRC32_D8.dcp
........\.............\.......\CRC32_D8.rds
........\.............\.......\CRC32_D8.tcl
........\.............\.......\CRC32_D8_utilization_synth.pb
........\.............\.......\CRC32_D8_util
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