pci core FPGA 7 series ip nuclear program

pci32_0_example\pci32_0_example.cache\wt\webtalk_pa.xml
...............\................srcs\constrs_1\imports\example_design\pci32_0_top.xdc
...............\....................\sim_1\imports\simulation\busrec.vhd
...............\....................\.....\.......\..........\functional\wave.do
...............\....................\.....\.......\..........\stimulus.vhd
...............\....................\.....\.......\..........\test_tb.vhd
...............\....................\.....\.......\..........\.iming\wave.do
...............\....................\.ources_1\imports\pci32_0\example_design_pci_top_xdc_7x_a7.txt
...............\....................\.........\.......\.......\pci32_0\example_design\pci32_0_top.vhd
...............\....................\.........\.......\.......\.......\..............\pci_lc.vhd
...............\....................\.........\.......\.......\.......\..............\userapp.vhd
...............\....................\.........\.p\pci32_0\doc\pci32_v5_0_changelog.txt
...............\....................\.........\..\.......\pci32_0.vho
...............\....................\.........\..\.......\pci32_0.xci
...............\....................\.........\..\.......\pci32_0.xml
...............\....................\.........\..\.......\......v5_0\hdl\pci32_v5_0_pkg.vhd
...............\....................\.........\..\.......\..........\...\pci32_v5_0_top.vhd
...............\....................\.........\..\.......\..........\...\pci32_v5_0_wrap.vhd
...............\....................\.........\..\.......\..........\...\source\pci_core\source\pci32_v5_0_addr.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_addr_vld.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_base_reg.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_cfg_remap.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_data_vld.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_dev_to.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_dr_bus.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_eot.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_eval.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_frame.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_full.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_header.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_irdy.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_i_idle.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_lat_timr.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_master.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_m_data.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_oe_frame.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_out_ce.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_out_sel.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_pci_ad.v
...............\....................\.........\..\.......\..........\...\......\........\......\pci32_v5_0_pci_adh.v
...............\....................\.......

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