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dual-port-RAM

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-05-08
  • Size : 626kb
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  • Author :qu xia******
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Introduction - If you have any usage issues, please Google them yourself
Use MegaWizard design of a dual-port RAM
Packet file list
(Preview for download)


新建文件夹
..........\Project
..........\.......\db
..........\.......\..\TOP.cbx.xml
..........\.......\..\TOP.cmp.rdb
..........\.......\..\TOP.db_info
..........\.......\..\TOP.eco.cdb
..........\.......\..\TOP.hif
..........\.......\..\TOP.map.hdb
..........\.......\..\TOP.map.qmsg
..........\.......\..\TOP.pre_map.hdb
..........\.......\..\TOP.sld_design_entry.sci
..........\.......\..\TOP.tis_db_list.ddb
..........\.......\Simulation
..........\.......\..........\altera_mf.v
..........\.......\..........\sim.do
..........\.......\..........\wave.do
..........\.......\TOP.flow.rpt
..........\.......\TOP.map.rpt
..........\.......\TOP.map.summary
..........\.......\TOP.qpf
..........\.......\TOP.qsf
..........\.......\TOP.qws
..........\.......\TOP_assignment_defaults.qdf
..........\Solution
..........\........\db
..........\........\..\altsyncram_87e1.tdf
..........\........\..\TOP.asm.qmsg
..........\........\..\TOP.cbx.xml
..........\........\..\TOP.cmp.cdb
..........\........\..\TOP.cmp.hdb
..........\........\..\TOP.cmp.kpt
..........\........\..\TOP.cmp.logdb
..........\........\..\TOP.cmp.rdb
..........\........\..\TOP.cmp.tdb
..........\........\..\TOP.cmp0.ddb
..........\........\..\TOP.db_info
..........\........\..\TOP.eco.cdb
..........\........\..\TOP.fit.qmsg
..........\........\..\TOP.hier_info
..........\........\..\TOP.hif
..........\........\..\TOP.lpc.html
..........\........\..\TOP.lpc.rdb
..........\........\..\TOP.lpc.txt
..........\........\..\TOP.map.cdb
..........\........\..\TOP.map.hdb
..........\........\..\TOP.map.logdb
..........\........\..\TOP.map.qmsg
..........\........\..\TOP.pre_map.cdb
..........\........\..\TOP.pre_map.hdb
..........\........\..\TOP.rtlv.hdb
..........\........\..\TOP.rtlv_sg.cdb
..........\........\..\TOP.rtlv_sg_swap.cdb
..........\........\..\TOP.sgdiff.cdb
..........\........\..\TOP.sgdiff.hdb
..........\........\..\TOP.sld_design_entry.sci
..........\........\..\TOP.sld_design_entry_dsc.sci
..........\........\..\TOP.syn_hier_info
..........\........\..\TOP.tan.qmsg
..........\........\..\TOP.tis_db_list.ddb
..........\........\..\TOP.tmw_info
..........\........\DualPortRAM.bsf
..........\........\DualPortRAM.v
..........\........\incremental_db
..........\........\..............\compiled_partitions
..........\........\..............\...................\TOP.root_partition.map.kpt
..........\........\..............\README
..........\........\Simulation
..........\........\..........\altera_mf.v
..........\........\..........\DualPortRAM.v
..........\........\..........\sim.do
..........\........\..........\TOP.v
..........\........\..........\TOP.vt
..........\........\..........\wave.do
..........\........\TOP.asm.rpt
..........\........\TOP.bdf
..........\........\TOP.done
..........\........\TOP.fit.rpt
..........\........\TOP.fit.smsg
..........\........\TOP.fit.summary
..........\........\TOP.flow.rpt
..........\........\TOP.map.rpt
..........\........\TOP.map.summary
..........\........\TOP.pin
..........\........\TOP.pof
..........\........\TOP.qpf
..........\........\TOP.qsf
..........\........\TOP.qws
..........\........\TOP.sof
..........\........\TOP.tan.rpt
..........\........\TOP.tan.summary
..........\........\TOP.v
..........\........\TOP.vt
..........\........\TOP.vwf
..........\........\TOP_assignment_defaults.qdf
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