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SOC_Code
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VHDL-FPGA-Verilog
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Update : 2015-05-17
Size : 92kb
Downloaded :0次
Author :
dan****
About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
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The source-code complement adder, multiplier, ROM design, such as PC counter of VHDL code in detail
Packet file list
(Preview for download)
SOC_Code设计实践\SOC_Code\01_串行加法器\cxjfq.ucf
................\........\.............\cxjfq.vhd
................\........\.2_并行加法器\bxjfq.ucf
................\........\.............\bxjfq.vhd
................\........\.3_数码管显示模块\data2seg.vhd
................\........\.................\seg_dis.vhd
................\........\.................\seg_dis_keyin.vhd
................\........\.................\smg.ucf
................\........\.4_原码两位乘\mul2.vhd
................\........\.5_布斯乘法器\ComplementalCodeMultiplexer8b.ucf
................\........\.............\ComplementalCodeMultiplexer8b.vhd
................\........\.6_阵列乘法器\and_2.vhd
................\........\.............\fau.vhd
................\........\.............\low_row.vhd
................\........\.............\mid_row.vhd
................\........\.............\mul8_0.vhd
................\........\.............\mul8_o.ucf
................\........\.............\test.vhd
................\........\.............\top_row.vhd
................\........\.7_加减交替除法器\a.ucf
................\........\.................\div.vhd
................\........\.8_ROM存储器\data2seg.vhd
................\........\............\myUCF.ucf
................\........\............\ROM.vhd
................\........\............\romfile.dat
................\........\............\seg_dis.vhd
................\........\............\top.vhd
................\........\.9_FIFO存储器\data2seg.vhd
................\........\.............\fifio_tb.vhd
................\........\.............\fifo_top.vhd
................\........\.............\myUCF.ucf
................\........\.............\seg_dis.vhd
................\........\.............\seg_dis_keyin.vhd
................\........\10_时钟模块设计\clk_gen.vhd
................\........\...............\testbench.vhd
................\........\.1_PC程序计数器设计\data2seg.vhd
................\........\...................\myUCF.ucf
................\........\...................\pc.vhd
................\........\...................\seg_dis.vhd
................\........\...................\seg_dis_keyin.vhd
................\........\.2_程序存储器ROM(4KB)\data2seg.vhd
................\........\.......................\myUCF.ucf
................\........\.......................\ROM.vhd
................\........\.......................\romfile.dat
................\........\.......................\seg_dis.vhd
................\........\.......................\top.vhd
................\........\.3_IR_Resgister\data2seg.vhd
................\........\...............\IR_module.vhd
................\........\...............\myUCF.ucf
................\........\...............\seg_dis.vhd
................\........\...............\seg_dis_keyin.vhd
................\........\.4_RN_Resgister\data2seg.vhd
................\........\...............\module_Rn.vhd
................\........\...............\myUCF.ucf
................\........\...............\seg_dis.vhd
................\........\...............\seg_dis_keyin.vhd
................\........\.5_算数逻辑单元ALU设计\data2seg.vhd
................\........\......................\myUCF.ucf
................\........\......................\seg_dis.vhd
................\........\......................\seg_dis_keyin.vhd
................\........\......................\unit74181.vhd
................\........\.6_数据存储器RAM设计\data2seg.vhd
................\........\....................\module_ram.vhd
................\........\....................\module_ram_tb.vhd
................\........\....................\myUCF.ucf
................\........\....................\seg_dis.vhd
................\........\....................\seg_dis_keyin.vhd
................\........\.7_堆栈指针SP设计\data2seg.vhd
................\........\.................\frediv.vhd
................\........\.................\module_sp.vhd
................\........\.................\myUCF.ucf
................\........\.................\seg_dis.vhd
................\........\.................\seg_dis_keyin.vhd
......
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