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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2015-05-19
  • Size : 238kb
  • Downloaded :0次
  • Author :刘****
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Introduction - If you have any usage issues, please Google them yourself
basys2 four digital timer 0 to 999.9 seconds
Packet file list
(Preview for download)


clock
.....\.lso
.....\_ngo
.....\....\netlist.lst
.....\_xmsgs
.....\......\bitgen.xmsgs
.....\......\map.xmsgs
.....\......\ngdbuild.xmsgs
.....\......\par.xmsgs
.....\......\pn_parser.xmsgs
.....\......\trce.xmsgs
.....\......\xst.xmsgs
.....\clock.bgn
.....\clock.bit
.....\clock.bld
.....\clock.cmd_log
.....\clock.drc
.....\clock.gise
.....\clock.lso
.....\clock.ncd
.....\clock.ngc
.....\clock.ngd
.....\clock.ngr
.....\clock.pad
.....\clock.par
.....\clock.pcf
.....\clock.prj
.....\clock.ptwx
.....\clock.stx
.....\clock.syr
.....\clock.twr
.....\clock.twx
.....\clock.ucf
.....\clock.unroutes
.....\clock.ut
.....\clock.vhd
.....\clock.xise
.....\clock.xpi
.....\clock.xst
.....\clock_bitgen.xwbt
.....\clock_envsettings.html
.....\clock_guide.ncd
.....\clock_map.map
.....\clock_map.mrp
.....\clock_map.ncd
.....\clock_map.ngm
.....\clock_map.xrpt
.....\clock_ngdbuild.xrpt
.....\clock_pad.csv
.....\clock_pad.txt
.....\clock_par.xrpt
.....\clock_summary.html
.....\clock_summary.xml
.....\clock_usage.xml
.....\clock_vhdl.prj
.....\clock_xst.xrpt
.....\ipcore_dir
.....\iseconfig
.....\.........\clock.projectmgr
.....\.........\clock.xreport
.....\usage_statistics_webtalk.html
.....\webtalk.log
.....\webtalk_pn.xml
.....\xlnx_auto_0_xdb
.....\...............\cst.xbcd
.....\xst
.....\...\dump.xst
.....\...\........\clock.prj
.....\...\........\.........\ngx
.....\...\........\.........\...\notopt
.....\...\........\.........\...\opt
.....\...\projnav.tmp
.....\...\work
.....\...\....\hdllib.ref
.....\...\....\hdpdeps.ref
.....\...\....\sub00
.....\...\....\.....\vhpl00.vho
.....\...\....\.....\vhpl01.vho
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