FPGA, ISE12.2, DDS the code, VHDL language

DDS\.recordref
...\accumulater.cmd_log
...\accumulater.edn
...\accumulater.htm
...\accumulater.prj
...\accumulater.sdc
...\accumulater.srs
...\ACCUMULATER.vhd
...\accumulater_open_file.tcl
...\accumulater_summary.html
...\address_convertor.cmd_log
...\address_convertor.edn
...\address_convertor.htm
...\address_convertor.prj
...\address_convertor.sdc
...\ADDRESS_CONVERTOR.vhd
...\address_convertor_open_file.tcl
...\ADDR_CHG.bmm
...\ADDR_CHG.cmd_log
...\ADDR_CHG.htm
...\ADDR_CHG.prj
...\ADDR_CHG.sdc
...\ADDR_CHG_open_file.tcl
...\AutoConstraint_data_convertor.sdc
...\AutoConstraint_DDS.sdc
...\clkd.cmd_log
...\clkd.edn
...\clkd.htm
...\clkd.prj
...\clkd.sdc
...\CLKD.vhd
...\clkd_open_file.tcl
...\data_convertor.cmd_log
...\data_convertor.edn
...\data_convertor.fse
...\data_convertor.htm
...\data_convertor.map
...\data_convertor.ncf
...\data_convertor.prj
...\data_convertor.sap
...\data_convertor.sdc
...\data_convertor.srd
...\data_convertor.srm
...\data_convertor.srr
...\data_convertor.srs
...\data_convertor.szr
...\DATA_CONVERTOR.vhd
...\data_convertor_compile.tcl
...\data_convertor_map.tcl
...\data_convertor_open_file.tcl
...\DDS.cmd_log
...\DDS.edn
...\DDS.fse
...\DDS.gise
...\DDS.htm
...\DDS.map
...\DDS.ncf
...\DDS.prj
...\DDS.sap
...\DDS.sdc
...\DDS.srd
...\DDS.srm
...\DDS.srr
...\DDS.srs
...\DDS.szr
...\DDS.vhd
...\DDS.xise
...\DDS_2.vhd
...\DDS_compile.tcl
...\DDS_map.tcl
...\DDS_open_file.tcl
...\DDS_summary.html
...\KONGZHIZI_summary.html
...\layer0.sro
...\layer0.tlg
...\lock.cmd_log
...\lock.edn
...\lock.htm
...\lock.prj
...\lock.sdc
...\LOCK.vhd
...\lock_open_file.tcl
...\MX_MUX.vhd
...\phase_adder.cmd_log
...\phase_adder.edn
...\phase_adder.htm
...\phase_adder.prj
...\phase_adder.sdc
...\PHASE_ADDER.vhd
...\phase_adder_open_file.tcl
...\phase_adder_summary.html
...\ROM.cmd_log
...\ROM.edn
...\ROM.htm
...\ROM.prj
...\ROM.sdc
...\ROM.vhd
...\ROM_open_file.tcl
...\rpt_data_convertor.areasrr
...\rpt_data_convertor_areasrr.htm

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