UART developement in VHDL

uart\clk_divider.vhd
....\clk_divider.vhd.bak
....\testbench\modelsim.ini
....\.........\vsim.wlf
....\.........\work\clk_divider\baudgen.dat
....\.........\....\...........\baudgen.dbs
....\.........\....\...........\_primary.dat
....\.........\....\...........\_primary.dbs
....\.........\....\uart\uart1.dat
....\.........\....\....\uart1.dbs
....\.........\....\....\_primary.dat
....\.........\....\....\_primary.dbs
....\.........\....\...._receiver\rcvr.dat
....\.........\....\.............\rcvr.dbs
....\.........\....\.............\_primary.dat
....\.........\....\.............\_primary.dbs
....\.........\....\.....test\test1.dat
....\.........\....\.........\test1.dbs
....\.........\....\.........\_primary.dat
....\.........\....\.........\_primary.dbs
....\.........\....\......ransmitter\xmit.dat
....\.........\....\................\xmit.dbs
....\.........\....\................\_primary.dat
....\.........\....\................\_primary.dbs
....\.........\....\_info
....\.........\....\.opt\vopt24mbv1
....\.........\....\....\vopt2z2dc8
....\.........\....\....\vopt36rgs1
....\.........\....\....\vopt6aca3q
....\.........\....\....\vopt6b9dir
....\.........\....\....\vopt6ka8v1
....\.........\....\....\voptat173q
....\.........\....\....\voptavy9ir
....\.........\....\....\voptdaq43q
....\.........\....\....\voptdt1yy7
....\.........\....\....\voptebk6ir
....\.........\....\....\voptgaqvy7
....\.........\....\....\vopthah0jm
....\.........\....\....\vopthv93ir
....\.........\....\....\voptknkxyg
....\.........\....\....\voptktcry7
....\.........\....\....\voptkyctc8
....\.........\....\....\voptmbz0ir
....\.........\....\....\voptqa2my7
....\.........\....\....\voptr6atyg
....\.........\....\....\voptre2qc8
....\.........\....\....\voptrvkwhr
....\.........\....\....\voptvj5hb3
....\.........\....\....\voptvyqkc8
....\.........\....\....\voptwnzqyg
....\.........\....\....\voptwves1q
....\.........\....\....\voptyjzev1
....\.........\....\....\voptzedhc8
....\.........\....\....\_deps
....\UART.vhd
....\UART_Receiver.vhd
....\UART_tb.vhd
....\UART_tb.vhd.bak
....\UART_Transmitter.vhd
....\UART_Transmitter.vhd.bak
....\testbench\work\clk_divider
....\.........\....\uart
....\.........\....\uart_receiver
....\.........\....\uart_test
....\.........\....\uart_transmitter
....\.........\....\_opt
....\.........\....\_temp
....\.........\work
....\testbench
uart

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