24 way serial ports to 1 serial port, including FIFO module,RX module,TX module, timer module, detection and control module, etc.. Verilog preparation

uart_server\db\uart_server.db_info
...........\..\uart_server.sld_design_entry.sci
...........\greybox_tmp\cbx_args.txt
...........\incremental_db\compiled_partitions\uart_server.db_info
...........\..............\README
...........\rx_fifo_module.qip
...........\source\cmd_control_module.v
...........\......\cmd_control_module.v.bak
...........\......\detect_module.v
...........\......\detect_module.v.bak
...........\......\divider.v.bak
...........\......\greybox_tmp\cbx_args.txt
...........\......\inter_control_module.v
...........\......\inter_control_module.v.bak
...........\......\IO_control.v.bak
...........\......\IO_control_module.v
...........\......\mytest.v
...........\......\mytest.v.bak
...........\......\power_on_delay_module.v
...........\......\power_on_delay_module.v.bak
...........\......\roll_control_module.v
...........\......\roll_control_module.v.bak
...........\......\rxcmd_control_module.v
...........\......\rxcmd_control_module.v.bak
...........\......\rxcmd_module.v
...........\......\rxcmd_module.v.bak
...........\......\rxd.v.bak
...........\......\rx_57600bps_module.v
...........\......\rx_57600bps_module.v.bak
...........\......\rx_bps_module.v
...........\......\rx_bps_module.v.bak
...........\......\rx_control_module.v
...........\......\rx_control_module.v.bak
...........\......\rx_counter_module.v
...........\......\rx_counter_module.v.bak
...........\......\rx_enable_control_module.v
...........\......\rx_enable_control_module.v.bak
...........\......\rx_fifo_module.qip
...........\......\rx_fifo_module.v
...........\......\rx_fifo_module_bb.v
...........\......\rx_fifo_module_inst.v
...........\......\rx_interface.v
...........\......\rx_interface.v.bak
...........\......\rx_module.v
...........\......\rx_module.v.bak
...........\......\rx_module_new.v.bak
...........\......\rx_top_control_module.v
...........\......\rx_top_control_module.v.bak
...........\......\rx_tx_interface_demo.v
...........\......\rx_tx_interface_demo.v.bak
...........\......\tx_bps_module.v
...........\......\tx_bps_module.v.bak
...........\......\tx_control_module.v
...........\......\tx_control_module.v.bak
...........\......\tx_fifo_module.qip
...........\......\tx_fifo_module.v
...........\......\tx_fifo_module_bb.v
...........\......\tx_fifo_module_inst.v
...........\......\tx_fifo_module_inst.v.bak
...........\......\tx_interface.v
...........\......\tx_interface.v.bak
...........\......\tx_module.v
...........\......\tx_top_control_module.v
...........\......\tx_top_control_module.v.bak
...........\......\uart.stp
...........\......\uart_interface_demo.v
...........\......\uart_interface_demo.v.bak
...........\......\use_IO.v.bak
...........\tcl\18_osh.tcl
...........\...\uart.parallel.txt
...........\tx_fifo_module.qip
...........\uart_server.asm.rpt
...........\uart_server.cdf
...........\uart_server.done
...........\uart_server.fit.rpt
...........\uart_server.fit.smsg
...........\uart_server.fit.summary
...........\uart_server.flow.rpt
...........\uart_server.jdi
...........\uart_server.map.rpt
...........\uart_server.map.smsg
...........\uart_server.map.summary
...........\uart_server.merge.rpt
...........\uart_server.out.sdc
...........\uart_server.pin
...........\uart_server.pof
...........\uart_server.qpf
...........\uart_server.qsf
...........\uart_server.sof
...........\uart_server.sta.rpt
...........\uart_server.sta.summary
...........\incremental_db\compiled_partitions
...........\source\greybox_tmp
...........\db
...........\greybox_tmp
...........\incremental_db
...........\source
...........\tcl
uart_server

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