SD card reader-writer source code. Prepared to use Verilog. Is pretty good. Be used for reference. In particular, the development of personnel SD card!

sdcard_mass_storage_controller
..............................\branches
..............................\........\README.txt
..............................\........\conf
..............................\........\....\authz
..............................\........\....\passwd
..............................\........\....\svnserve.conf
..............................\........\db
..............................\........\..\current
..............................\........\..\format
..............................\........\..\fs-type
..............................\........\..\fsfs.conf
..............................\........\..\min-unpacked-rev
..............................\........\..\rep-cache.db
..............................\........\..\revprops
..............................\........\..\........\0
..............................\........\..\........\.\0
..............................\........\..\revs
..............................\........\..\....\0
..............................\........\..\....\.\0
..............................\........\..\transactions
..............................\........\..\txn-current
..............................\........\..\txn-current-lock
..............................\........\..\txn-protorevs
..............................\........\..\uuid
..............................\........\..\write-lock
..............................\........\format
..............................\........\hooks
..............................\........\.....\post-commit.tmpl
..............................\........\.....\post-lock.tmpl
..............................\........\.....\post-revprop-change.tmpl
..............................\........\.....\post-unlock.tmpl
..............................\........\.....\pre-commit.tmpl
..............................\........\.....\pre-lock.tmpl
..............................\........\.....\pre-revprop-change.tmpl
..............................\........\.....\pre-unlock.tmpl
..............................\........\.....\start-commit.tmpl
..............................\........\locks
..............................\........\.....\db-logs.lock
..............................\........\.....\db.lock
..............................\format
..............................\tags
..............................\trunk
..............................\.....\README.txt
..............................\.....\backend
..............................\.....\.......\Actel
..............................\.....\.......\.....\Block
..............................\.....\.......\.....\.....\versatile_fifo_dptam_dw
..............................\.....\.......\.....\.....\.......................\compile_report.log
..............................\.....\.......\.....\.....\.......................\datasheet_report.log
..............................\.....\.......\.....\.....\.......................\global_report.log
..............................\.....\.......\.....\.....\.......................\header_report.log
..............................\.....\.......\.....\.....\.......................\interface_report.log
..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw.cdb
..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw.cxf
..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw_pre.v
..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw_sim.v
..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw_syn.v
..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw_usedLocations.pdc
..............................\.....\.......\.....\proasic3_redused.v
..............................\.....\bench
..............................\.....\.....\sdc_dma
..............................\.....\.....\.......\verilog
..............................\.....\.....\.......\.......\sdModel.v
..............................\.....\.....\.......\.......\sd_contro

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