DVI demo write by Verilog-HDL，test by modelsim.

dvi_demo\ucf\dvi_demo.ucf
........\...\vtc_demo.ucf
........\rtl\dvi_demo.v
........\...\rx\phsaligner.v
........\...\..\chnlbond.v
........\...\..\decode.v
........\...\..\dvi_decoder.v
........\...\..\serdes_1_to_5_diff_data.v
........\...\tx\convert_30to15_fifo.v
........\...\..\dvi_encoder.v
........\...\..\encode.v
........\...\..\serdes_n_to_1.v
........\...\..\vtc_demo.v
........\...\..\dvi_encoder_top.v
........\...\common\DRAM16XN.v
........\...\......\hdclrbar.v
........\...\......\timing.v
........\...\......\debnce.v
........\...\......\synchro.v
........\...\......\dcmspi.v
........\...\......\debnce.v.bak
........\...\dvi_tp1.v
........\...\glbl.v
........\...\vtc_demo.v
........\...\dvi_tp.v
........\...\dvi_tp.v.bak
........\work\_info
........\....\.temp\vlogfbsv6n
........\....\_vmake
........\....\chnlbond\_primary.vhd
........\....\........\_primary.dbs
........\....\........\_primary.dat
........\....\........\verilog.asm
........\....\........\verilog.rw
........\....\decode\_primary.vhd
........\....\......\_primary.dbs
........\....\......\_primary.dat
........\....\......\verilog.asm
........\....\......\verilog.rw
........\....\.vi_decoder\_primary.vhd
........\....\...........\_primary.dbs
........\....\...........\_primary.dat
........\....\...........\verilog.asm
........\....\...........\verilog.rw
........\....\phsaligner\_primary.vhd
........\....\..........\_primary.dbs
........\....\..........\_primary.dat
........\....\..........\verilog.asm
........\....\..........\verilog.rw
........\....\serdes_1_to_5_diff_data\_primary.vhd
........\....\.......................\_primary.dbs
........\....\.......................\_primary.dat
........\....\.......................\verilog.asm
........\....\.......................\verilog.rw
........\....\convert_30to15_fifo\_primary.vhd
........\....\...................\_primary.dbs
........\....\...................\_primary.dat
........\....\...................\verilog.asm
........\....\...................\verilog.rw
........\....\dvi_encoder\_primary.vhd
........\....\...........\_primary.dbs
........\....\...........\_primary.dat
........\....\...........\verilog.asm
........\....\...........\verilog.rw
........\....\..........._top\_primary.vhd
........\....\...............\_primary.dbs
........\....\...............\_primary.dat
........\....\encode\_primary.vhd
........\....\......\_primary.dbs
........\....\......\_primary.dat
........\....\......\verilog.asm
........\....\......\verilog.rw
........\....\serdes_n_to_1\_primary.vhd
........\....\.............\_primary.dbs
........\....\.............\_primary.dat
........\....\.............\verilog.asm
........\....\.............\verilog.rw
........\....\vtc_demo\_primary.vhd
........\....\........\_primary.dbs
........\....\........\_primary.dat
........\....\........\verilog.asm
........\....\........\verilog.rw
........\....\dvi_demo\_primary.vhd
........\....\........\_primary.dbs
........\....\........\_primary.dat
........\....\.cmspi\_primary.vhd
........\....\......\_primary.dbs
........\....\......\_primary.dat
........\....\......\verilog.asm
........\....\......\verilog.rw
........\....\.ebnce\_primary.vhd
........\....\......\_primary.dbs
........\....\......\_primary.dat
........\....\......\verilog.asm
........\....\......\verilog.rw
........\....\@d@r@a@m16@x@n\_primary.vhd
........\....\..............\_primary.dbs
........\....\..............\_primary.dat
........\....\..............\verilog.asm
........\....\..............\verilog.rw

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