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  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-06-26
  • Size : 543kb
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  • Author :刘***
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Introduction - If you have any usage issues, please Google them yourself
Verilog language, the method of the dividing timer is displayed on the digital display 0-59 seconds.
Packet file list
(Preview for download)


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.....\Waveform1.vwf
.....\clock.asm.rpt
.....\clock.done
.....\clock.eda.rpt
.....\clock.fit.rpt
.....\clock.fit.summary
.....\clock.flow.rpt
.....\clock.map.rpt
.....\clock.map.smsg
.....\clock.map.summary
.....\clock.pin
.....\clock.pof
.....\clock.qpf
.....\clock.qsf
.....\clock.qws
.....\clock.sim.rpt
.....\clock.tan.rpt
.....\clock.tan.summary
.....\clock.v
.....\clock.v.bak
.....\clock.vwf
.....\clock_nativelink_simulation.rpt
.....\db
.....\..\add_sub_3kh.tdf
.....\..\add_sub_7ph.tdf
.....\..\add_sub_8ph.tdf
.....\..\add_sub_m9c.tdf
.....\..\add_sub_n9c.tdf
.....\..\add_sub_nnh.tdf
.....\..\add_sub_o9c.tdf
.....\..\add_sub_p9c.tdf
.....\..\add_sub_pnh.tdf
.....\..\add_sub_q9c.tdf
.....\..\alt_u_div_lke.tdf
.....\..\clock.asm.qmsg
.....\..\clock.cbx.xml
.....\..\clock.cmp.cdb
.....\..\clock.cmp.hdb
.....\..\clock.cmp.logdb
.....\..\clock.cmp.rdb
.....\..\clock.cmp.tdb
.....\..\clock.cmp0.ddb
.....\..\clock.db_info
.....\..\clock.eco.cdb
.....\..\clock.eda.qmsg
.....\..\clock.eds_overflow
.....\..\clock.fit.qmsg
.....\..\clock.fnsim.cdb
.....\..\clock.fnsim.hdb
.....\..\clock.fnsim.qmsg
.....\..\clock.hier_info
.....\..\clock.hif
.....\..\clock.lpc.html
.....\..\clock.lpc.rdb
.....\..\clock.lpc.txt
.....\..\clock.map.cdb
.....\..\clock.map.hdb
.....\..\clock.map.logdb
.....\..\clock.map.qmsg
.....\..\clock.pre_map.cdb
.....\..\clock.pre_map.hdb
.....\..\clock.rpp.qmsg
.....\..\clock.rtlv.hdb
.....\..\clock.rtlv_sg.cdb
.....\..\clock.rtlv_sg_swap.cdb
.....\..\clock.sgate.rvd
.....\..\clock.sgate_sm.rvd
.....\..\clock.sgdiff.cdb
.....\..\clock.sgdiff.hdb
.....\..\clock.sim.cvwf
.....\..\clock.sim.hdb
.....\..\clock.sim.qmsg
.....\..\clock.sim.rdb
.....\..\clock.simfam
.....\..\clock.sld_design_entry.sci
.....\..\clock.sld_design_entry_dsc.sci
.....\..\clock.syn_hier_info
.....\..\clock.tan.qmsg
.....\..\clock.tis_db_list.ddb
.....\..\clock.tmw_info
.....\..\lpm_divide_02m.tdf
.....\..\lpm_divide_3ql.tdf
.....\..\prev_cmp_clock.asm.qmsg
.....\..\prev_cmp_clock.eda.qmsg
.....\..\prev_cmp_clock.fit.qmsg
.....\..\prev_cmp_clock.map.qmsg
.....\..\prev_cmp_clock.qmsg
.....\..\prev_cmp_clock.sim.qmsg
.....\..\prev_cmp_clock.tan.qmsg
.....\..\sign_div_unsign_9kh.tdf
.....\..\wed.wsf
.....\incremental_db
.....\..............\README
.....\..............\compiled_partitions
.....\..............\...................\clock.root_partition.map.kpt
.....\simulation
.....\..........\modelsim
.....\..........\........\clock.sft
.....\..........\........\clock.vo
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