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superdigitalclock

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-06-28
  • Size : 1.43mb
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  • Author :黄****
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Introduction - If you have any usage issues, please Google them yourself
This is based on the FPGA development board BASYS2 a intelligent digital clock, can divide three patterns: the minutes and seconds, of a second.Through the button switch mode and in digital tube display
Packet file list
(Preview for download)


superdigitalclock\.lso
.................\but_dff.bld
.................\but_dff.cmd_log
.................\but_dff.lso
.................\but_dff.ncd
.................\but_dff.ngc
.................\but_dff.ngd
.................\but_dff.ngr
.................\but_dff.par
.................\but_dff.pcf
.................\but_dff.prj
.................\but_dff.stx
.................\but_dff.syr
.................\but_dff.twr
.................\but_dff.twx
.................\but_dff.unroutes
.................\but_dff.vhd
.................\but_dff.xst
.................\but_dff_envsettings.html
.................\but_dff_guide.ncd
.................\but_dff_isim_beh.exe
.................\but_dff_map.map
.................\but_dff_map.mrp
.................\but_dff_map.ncd
.................\but_dff_map.ngm
.................\but_dff_pad.csv
.................\but_dff_pad.txt
.................\but_dff_stx_beh.prj
.................\but_dff_summary.html
.................\but_dff_vhdl.prj
.................\but_dff_xst.xrpt
.................\clk100hz.bld
.................\clk100hz.cmd_log
.................\clk100hz.lso
.................\clk100hz.ncd
.................\clk100hz.ngc
.................\clk100hz.ngd
.................\clk100hz.ngr
.................\clk100hz.par
.................\clk100hz.pcf
.................\clk100hz.prj
.................\clk100hz.stx
.................\clk100hz.syr
.................\clk100hz.twr
.................\clk100hz.twx
.................\clk100hz.unroutes
.................\clk100hz.vhd
.................\clk100hz.xst
.................\clk100hz_guide.ncd
.................\clk100hz_isim_beh.exe
.................\clk100hz_map.map
.................\clk100hz_map.mrp
.................\clk100hz_map.ncd
.................\clk100hz_map.ngm
.................\clk100hz_pad.csv
.................\clk100hz_pad.txt
.................\clk100hz_stx_beh.prj
.................\clk100hz_tb.vhd
.................\clk100hz_tb_isim_beh.exe
.................\clk100hz_tb_stx_beh.prj
.................\clk100hz_vhdl.prj
.................\clk100hz_xst.xrpt
.................\clk1hz.vhd
.................\clk1hz_guide.ncd
.................\clk1hz_tb.vhd
.................\clkscan_guide.ncd
.................\clkscan_tb.vhd
.................\cntminute_tb.vhd
.................\cntminute_tb_isim_beh.exe
.................\cntminute_tb_stx_beh.prj
.................\cnt_10minute.bld
.................\cnt_10minute.cmd_log
.................\cnt_10minute.lso
.................\cnt_10minute.ncd
.................\cnt_10minute.ngc
.................\cnt_10minute.ngd
.................\cnt_10minute.ngr
.................\cnt_10minute.par
.................\cnt_10minute.pcf
.................\cnt_10minute.prj
.................\cnt_10minute.stx
.................\cnt_10minute.syr
.................\cnt_10minute.twr
.................\cnt_10minute.twx
.................\cnt_10minute.unroutes
.................\cnt_10minute.vhd
.................\cnt_10minute.xst
.................\cnt_10minute_envsettings.html
.................\cnt_10minute_guide.ncd
.................\cnt_10minute_map.map
.................\cnt_10minute_map.mrp
.................\cnt_10minute_map.ncd
.................\cnt_10minute_map.ngm
.................\cnt_10minute_pad.csv
.................\cnt_10minute_pad.txt
.................\cnt_10minute_summary.html
.................\cnt_10minute_vhdl.prj
.................\cnt_10minute_xst.xrpt
.................\cnt_minute.bld
.................\cnt_minute.cmd_log
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