Chip design based on Xilinx s network V5 MAC layer interface, can communicate with the computer network, can be tailored to customize according to their needs, the board has passed the actual test.

emac_standard
.............\.recordref
.............\.recordref_modgen
.............\AutoConstraint_v5_emac_v1_5_example_design.sdc
.............\_mh_info
.............\_verilog_hintfile
.............\_xmsgs
.............\......\pn_parser.xmsgs
.............\backup
.............\client
.............\......\address_swap_module_8.vhd
.............\......\fifo
.............\......\....\eth_fifo_8.vhd
.............\......\....\rx_client_fifo_8.vhd
.............\......\....\tx_client_fifo_8.vhd
.............\coreip
.............\dm
.............\..\layer0.xdm
.............\emac_standard.gise
.............\emac_standard.xise
.............\ipcore_dir
.............\..........\_xmsgs
.............\..........\......\cg.xmsgs
.............\..........\coregen.log
.............\..........\create_GTP.tcl
.............\..........\tmp
.............\..........\...\_cg
.............\..........\...\...\xil_11192_5.in
.............\..........\...\...\xil_11192_5.out
.............\iseconfig
.............\.........\emac_standard.projectmgr
.............\.........\v5_emac_v1_5_example_design.xreport
.............\layer0.srs
.............\layer0.tlg
.............\physical
.............\........\gtp_dual_1000X.vhd
.............\........\rocketio_wrapper_gtp.vhd
.............\........\rocketio_wrapper_gtp_tile.vhd
.............\........\rx_elastic_buffer.vhd
.............\physical_plus
.............\.............\syntmp
.............\rpt_v5_emac_v1_5_example_design.areasrr
.............\rpt_v5_emac_v1_5_example_design_areasrr.htm
.............\run_ise.tcl
.............\run_options.txt
.............\scratchproject.prs
.............\stdout.log
.............\synlog
.............\......\report
.............\......\......\v5_emac_v1_5_example_design_compiler_notes.txt
.............\......\......\v5_emac_v1_5_example_design_compiler_runstatus.xml
.............\......\......\v5_emac_v1_5_example_design_compiler_warnings.txt
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_area_report.xml
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_errors.txt
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_generated_clk.rpt
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_hier_area.csv
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_hier_area_report.xml
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_notes.txt
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_opt_report.xml
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_resourceusage.rpt
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_runstatus.xml
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_timing_report.xml
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_warnings.txt
.............\......\......\v5_emac_v1_5_example_design_premap_errors.txt
.............\......\......\v5_emac_v1_5_example_design_premap_notes.txt
.............\......\......\v5_emac_v1_5_example_design_premap_runstatus.xml
.............\......\......\v5_emac_v1_5_example_design_premap_warnings.txt
.............\......\v5_emac_v1_5_example_design_fpga_mapper.srr
.............\......\v5_emac_v1_5_example_design_fpga_mapper.srr_Min
.............\......\v5_emac_v1_5_example_design_fpga_mapper.szr
.............\......\v5_emac_v1_5_example_design_premap.srr
.............\......\v5_emac_v1_5_example_design_premap.szr
.............\synplicity.ucf
.............\syntmp
.............\......\cmdrec_compiler.log
.............\......\cmdrec_fpga_mapper.log
.............\......\cmdrec_premap.log
.............\......\namekey.txt
.............\......\run_option.xml
.............\......\unisim.tlg
.............\......\unisim.v
.............\......\v5_emac_v1_5_example_design.msg
.............\......\v5_emac_v1_5_example_design.plg
.............\synwork
.............\.......\v5_emac_v1_5_example_design_compiler.srs
.............\.......\v5_emac_v1_5_example_design_premap.fse
.............\.......\v5_emac_v1_5_example_design_premap.srd
.............\

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