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  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-07-04
  • Size : 1.41mb
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  • Author :陈***
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Introduction - If you have any usage issues, please Google them yourself
Direct digital frequency synthesizer
Packet file list
(Preview for download)


db\add_sub_pve.tdf
..\altsyncram_1da1.tdf
..\altsyncram_2491.tdf
..\altsyncram_89a1.tdf
..\altsyncram_g491.tdf
..\DDS.asm.qmsg
..\DDS.cbx.xml
..\DDS.cmp.bpm
..\DDS.cmp.cdb
..\DDS.cmp.ecobp
..\DDS.cmp.hdb
..\DDS.cmp.logdb
..\DDS.cmp.rdb
..\DDS.cmp_bb.cdb
..\DDS.cmp_bb.hdb
..\DDS.cmp_bb.logdb
..\DDS.cmp_bb.rcf
..\DDS.dbp
..\DDS.db_info
..\DDS.eco.cdb
..\DDS.eds_overflow
..\DDS.fit.qmsg
..\DDS.fnsim.cdb
..\DDS.fnsim.hdb
..\DDS.fnsim.qmsg
..\DDS.hier_info
..\DDS.hif
..\DDS.map.bpm
..\DDS.map.cdb
..\DDS.map.ecobp
..\DDS.map.hdb
..\DDS.map.logdb
..\DDS.map.qmsg
..\DDS.map_bb.cdb
..\DDS.map_bb.hdb
..\DDS.map_bb.logdb
..\DDS.pre_map.cdb
..\DDS.pre_map.hdb
..\DDS.psp
..\DDS.pss
..\DDS.rtlv.hdb
..\DDS.rtlv_sg.cdb
..\DDS.rtlv_sg_swap.cdb
..\DDS.sgdiff.cdb
..\DDS.sgdiff.hdb
..\DDS.signalprobe.cdb
..\DDS.sim.cvwf
..\DDS.sim.hdb
..\DDS.sim.qmsg
..\DDS.sim.rdb
..\DDS.sim_ori.vwf
..\DDS.sld_design_entry.sci
..\DDS.sld_design_entry_dsc.sci
..\DDS.sta.qmsg
..\DDS.sta.rdb
..\DDS.syn_hier_info
..\DDS.tiscmp0.ddb
..\DDS.tiscmp2.ddb
..\mux_p7e.tdf
..\mux_s7e.tdf
..\prev_cmp_DDS.asm.qmsg
..\prev_cmp_DDS.fit.qmsg
..\prev_cmp_DDS.map.qmsg
..\prev_cmp_DDS.sim.qmsg
..\prev_cmp_DDS.sta.qmsg
..\wed.wsf
2FP.bdf
2FP.bsf
2FP.vwf
3FP.bdf
3FP.bsf
3FP.vwf
8FP.bdf
8FP.bsf
8FP.vwf
1000FP.bdf
1000FP.bsf
1000FP.vwf
BCD-2BIN.bdf
BCD-2BIN.bsf
BCD-2BIN.vwf
cepindianlu.bdf
cepindianlu.bsf
cepindianlu.vwf
cosine.bdf
cosine.bsf
DDS.asm.rpt
DDS.cdf
DDS.done
DDS.dpf
DDS.fit.rpt
DDS.fit.rptPreview
DDS.fit.smsg
DDS.fit.summary
DDS.flow.rpt
DDS.map.rpt
DDS.map.summary
DDS.pin
DDS.pof
DDS.qpf
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