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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-07-07
  • Size : 3.52mb
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  • Author :杨****
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Introduction - If you have any usage issues, please Google them yourself
VGA layer concept of the FPGA can well understand VGA works
Packet file list
(Preview for download)


vga_3
.....\PLLJ_PLLSPE_INFO.txt
.....\PLL_40m.ppf
.....\PLL_40m.qip
.....\PLL_40m.v
.....\PLL_40m_bb.v
.....\PLL_40m_inst.v
.....\db
.....\..\PLL_40m_altpll.v
.....\..\altsyncram_5c91.tdf
.....\..\altsyncram_as91.tdf
.....\..\logic_util_heursitic.dat
.....\..\prev_cmp_vga_moudle.qmsg
.....\..\vga_moudle.amm.cdb
.....\..\vga_moudle.asm.qmsg
.....\..\vga_moudle.asm.rdb
.....\..\vga_moudle.asm_labs.ddb
.....\..\vga_moudle.cbx.xml
.....\..\vga_moudle.cmp.bpm
.....\..\vga_moudle.cmp.cdb
.....\..\vga_moudle.cmp.hdb
.....\..\vga_moudle.cmp.kpt
.....\..\vga_moudle.cmp.logdb
.....\..\vga_moudle.cmp.rdb
.....\..\vga_moudle.cmp_merge.kpt
.....\..\vga_moudle.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
.....\..\vga_moudle.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
.....\..\vga_moudle.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
.....\..\vga_moudle.db_info
.....\..\vga_moudle.fit.qmsg
.....\..\vga_moudle.hier_info
.....\..\vga_moudle.hif
.....\..\vga_moudle.idb.cdb
.....\..\vga_moudle.lpc.html
.....\..\vga_moudle.lpc.rdb
.....\..\vga_moudle.lpc.txt
.....\..\vga_moudle.map.bpm
.....\..\vga_moudle.map.cdb
.....\..\vga_moudle.map.hdb
.....\..\vga_moudle.map.kpt
.....\..\vga_moudle.map.logdb
.....\..\vga_moudle.map.qmsg
.....\..\vga_moudle.map_bb.cdb
.....\..\vga_moudle.map_bb.hdb
.....\..\vga_moudle.map_bb.logdb
.....\..\vga_moudle.pre_map.cdb
.....\..\vga_moudle.pre_map.hdb
.....\..\vga_moudle.rpp.qmsg
.....\..\vga_moudle.rtlv.hdb
.....\..\vga_moudle.rtlv_sg.cdb
.....\..\vga_moudle.rtlv_sg_swap.cdb
.....\..\vga_moudle.sgate.rvd
.....\..\vga_moudle.sgate_sm.rvd
.....\..\vga_moudle.sgdiff.cdb
.....\..\vga_moudle.sgdiff.hdb
.....\..\vga_moudle.sld_design_entry.sci
.....\..\vga_moudle.sld_design_entry_dsc.sci
.....\..\vga_moudle.smart_action.txt
.....\..\vga_moudle.sta.qmsg
.....\..\vga_moudle.sta.rdb
.....\..\vga_moudle.sta_cmp.8_slow_1200mv_85c.tdb
.....\..\vga_moudle.syn_hier_info
.....\..\vga_moudle.tis_db_list.ddb
.....\..\vga_moudle.tiscmp.fast_1200mv_0c.ddb
.....\..\vga_moudle.tiscmp.fastest_slow_1200mv_0c.ddb
.....\..\vga_moudle.tiscmp.fastest_slow_1200mv_85c.ddb
.....\..\vga_moudle.tiscmp.slow_1200mv_0c.ddb
.....\..\vga_moudle.tiscmp.slow_1200mv_85c.ddb
.....\..\vga_moudle.tmw_info
.....\greybox_tmp
.....\...........\cbx_args.txt
.....\incremental_db
.....\..............\README
.....\..............\compiled_partitions
.....\..............\...................\vga_moudle.db_info
.....\..............\...................\vga_moudle.root_partition.cmp.cdb
.....\..............\...................\vga_moudle.root_partition.cmp.dfp
.....\..............\...................\vga_moudle.root_partition.cmp.hdb
.....\..............\...................\vga_moudle.root_partition.cmp.kpt
.....\..............\...................\vga_moudle.root_partition.cmp.logdb
.....\..............\...................\vga_moudle.root_partition.cmp.rcfdb
.....\..............\...................\vga_moudle.root_partition.map.cdb
.....\..............\...................\vga_moudle.root_partition.map.dpi
.....\..............\...................\vga_moudle.root_partition.map.hbdb.cdb
.....\..............\...................\vga_moudle.root_partition.map.hbdb.hb_info
.....\..............\...................\vga_moudle.root_partition.map.hbdb.hdb
.....\..............\...................\vga_moudle.root_partition.map.hbdb.sig
.....\..............\...................\vga_moudle.root_partition.map.hdb
.....\..............\...................\vga_moudle.root_partition.map.kpt
.....\my_ziku.mif
.....\rom_ziku.qip
.....\rom_ziku.v
.....\rom_ziku_bb.v
.....\rom_ziku_inst.v
.....\sync_module.v
.....\vga_control_module.v
.....\vga_control_module.v.bak
.....\vga_module.v
.....\vga_module.v.bak
.....\vga_moudle.asm.rpt
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