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shuzishizhong

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-07-09
  • Size : 3.75mb
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Introduction - If you have any usage issues, please Google them yourself
DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board digital display seconds (60s), points (60min), hours (24hours) time . And has a function to manually adjust the time
Packet file list
(Preview for download)


shuzishizhong\cnt10.vhd
.............\cnt10.vhd.bak
.............\cnt24.vhd
.............\cnt24.vhd.bak
.............\cnt6.vhd
.............\cnt6.vhd.bak
.............\db\logic_util_heursitic.dat
.............\..\prev_cmp_wk2.qmsg
.............\..\wk2.amm.cdb
.............\..\wk2.asm.qmsg
.............\..\wk2.asm.rdb
.............\..\wk2.asm_labs.ddb
.............\..\wk2.cbx.xml
.............\..\wk2.cmp.bpm
.............\..\wk2.cmp.cdb
.............\..\wk2.cmp.hdb
.............\..\wk2.cmp.kpt
.............\..\wk2.cmp.logdb
.............\..\wk2.cmp.rdb
.............\..\wk2.cmp_merge.kpt
.............\..\wk2.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
.............\..\wk2.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
.............\..\wk2.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
.............\..\wk2.db_info
.............\..\wk2.eda.qmsg
.............\..\wk2.fit.qmsg
.............\..\wk2.hier_info
.............\..\wk2.hif
.............\..\wk2.idb.cdb
.............\..\wk2.lpc.html
.............\..\wk2.lpc.rdb
.............\..\wk2.lpc.txt
.............\..\wk2.map.bpm
.............\..\wk2.map.cdb
.............\..\wk2.map.hdb
.............\..\wk2.map.kpt
.............\..\wk2.map.logdb
.............\..\wk2.map.qmsg
.............\..\wk2.map_bb.cdb
.............\..\wk2.map_bb.hdb
.............\..\wk2.map_bb.logdb
.............\..\wk2.pre_map.cdb
.............\..\wk2.pre_map.hdb
.............\..\wk2.rtlv.hdb
.............\..\wk2.rtlv_sg.cdb
.............\..\wk2.rtlv_sg_swap.cdb
.............\..\wk2.sgdiff.cdb
.............\..\wk2.sgdiff.hdb
.............\..\wk2.sld_design_entry.sci
.............\..\wk2.sld_design_entry_dsc.sci
.............\..\wk2.smart_action.txt
.............\..\wk2.sta.qmsg
.............\..\wk2.sta.rdb
.............\..\wk2.sta_cmp.7_slow_1200mv_85c.tdb
.............\..\wk2.syn_hier_info
.............\..\wk2.tiscmp.fast_1200mv_0c.ddb
.............\..\wk2.tiscmp.slow_1200mv_0c.ddb
.............\..\wk2.tiscmp.slow_1200mv_85c.ddb
.............\..\wk2.tis_db_list.ddb
.............\display.vhd
.............\display.vhd.bak
.............\incremental_db\compiled_partitions\wk2.db_info
.............\..............\...................\wk2.root_partition.cmp.cdb
.............\..............\...................\wk2.root_partition.cmp.dfp
.............\..............\...................\wk2.root_partition.cmp.hdb
.............\..............\...................\wk2.root_partition.cmp.kpt
.............\..............\...................\wk2.root_partition.cmp.logdb
.............\..............\...................\wk2.root_partition.cmp.rcfdb
.............\..............\...................\wk2.root_partition.map.cdb
.............\..............\...................\wk2.root_partition.map.dpi
.............\..............\...................\wk2.root_partition.map.hbdb.cdb
.............\..............\...................\wk2.root_partition.map.hbdb.hb_info
.............\..............\...................\wk2.root_partition.map.hbdb.hdb
.............\..............\...................\wk2.root_partition.map.hbdb.sig
.............\..............\...................\wk2.root_partition.map.hdb
.............\..............\...................\wk2.root_partition.map.kpt
.............\..............\README
.............\sim\gate_work\wk2\structure.dat
.............\...\.........\...\structure.dbs
.............\...\.........\...\structure.prw
.............\...\.........\...\structure.psm
.............\...\.........\...\_primary.dat
.............\...\.........\...\_primary.dbs
.............\...\.........\..._vhd_tst\wk2_arch.dat
.............\...\.........\...........\wk2_arch.dbs
.............\...\.........\...........\wk2_arch.prw
.............\...\.........\...........\wk2_arch.psm
.............\...\.........\...........\_primary.dat
.............\...\.........\...........\_primary.dbs
.............\...\.........\_info
.............\...\.........\_vmake
.............\...\modelsim.ini
.............\...\msim_transcript
.............\...\transcript
.............\...\vsim.wlf
.............\...\wk2.sft
...........
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