This is a simple VHDL based program for beginners to write a rich electronic clock.

0714
....\db
....\..\d_clk.asm.qmsg
....\..\d_clk.cbx.xml
....\..\d_clk.cmp.cdb
....\..\d_clk.cmp.hdb
....\..\d_clk.cmp.kpt
....\..\d_clk.cmp.logdb
....\..\d_clk.cmp.rdb
....\..\d_clk.cmp.tdb
....\..\d_clk.cmp0.ddb
....\..\d_clk.dbp
....\..\d_clk.db_info
....\..\d_clk.eco.cdb
....\..\d_clk.eds_overflow
....\..\d_clk.fit.qmsg
....\..\d_clk.hier_info
....\..\d_clk.hif
....\..\d_clk.map.cdb
....\..\d_clk.map.hdb
....\..\d_clk.map.logdb
....\..\d_clk.map.qmsg
....\..\d_clk.pre_map.cdb
....\..\d_clk.pre_map.hdb
....\..\d_clk.psp
....\..\d_clk.rtlv.hdb
....\..\d_clk.rtlv_sg.cdb
....\..\d_clk.rtlv_sg_swap.cdb
....\..\d_clk.sgdiff.cdb
....\..\d_clk.sgdiff.hdb
....\..\d_clk.signalprobe.cdb
....\..\d_clk.sim.hdb
....\..\d_clk.sim.qmsg
....\..\d_clk.sim.rdb
....\..\d_clk.sim.vwf
....\..\d_clk.sld_design_entry.sci
....\..\d_clk.sld_design_entry_dsc.sci
....\..\d_clk.syn_hier_info
....\..\d_clk.tan.qmsg
....\..\wed.zsf
....\d_clk.asm.rpt
....\d_clk.done
....\d_clk.dpf
....\d_clk.fit.rpt
....\d_clk.fit.smsg
....\d_clk.fit.summary
....\d_clk.flow.rpt
....\d_clk.map.rpt
....\d_clk.map.summary
....\d_clk.pin
....\d_clk.pof
....\d_clk.qpf
....\d_clk.qsf
....\d_clk.qws
....\d_clk.sim.rpt
....\d_clk.sof
....\d_clk.tan.rpt
....\d_clk.tan.summary
....\d_clk.vhd
....\d_clk.vwf

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