ddr2 of Verilog code, including timing control, data is read using verilog prepared ddr2 controller board on spartan6 be verified, the successful implementation of the FPGA and DDR2 communications.

DDR2-verilog
............\Params.v
............\altclklock.v
............\chart
............\.....\图9-16.bmp
............\.....\图9-17.bmp
............\.....\图9-19.bmp
............\.....\图9-20.bmp
............\.....\图9-22.bmp
............\.....\图9-23.bmp
............\.....\图9-26.bmp
............\.....\图9-27.bmp
............\ddr.cr.mti
............\ddr.mpf
............\ddr_Command.v
............\ddr_control_interface.v
............\ddr_data_path.v
............\ddr_sdram.v
............\ddr_sdram_tb.v
............\note.txt
............\pll1.v
............\transcript
............\vsim.wlf
............\wave
............\....\ddr_command.bmp
............\....\ddr_control_interface.bmp
............\....\ddr_data_path.bmp
............\....\ddr_sdram.bmp
............\....\ddr_sdram_tb.bmp
............\work
............\....\_info
............\....\altclklock
............\....\..........\_primary.dat
............\....\..........\_primary.vhd
............\....\..........\verilog.asm
............\....\ddr_command
............\....\...........\_primary.dat
............\....\...........\_primary.vhd
............\....\...........\verilog.asm
............\....\ddr_control_interface
............\....\.....................\_primary.dat
............\....\.....................\_primary.vhd
............\....\.....................\verilog.asm
............\....\ddr_data_path
............\....\.............\_primary.dat
............\....\.............\_primary.vhd
............\....\.............\verilog.asm
............\....\ddr_sdram
............\....\.........\_primary.dat
............\....\.........\_primary.vhd
............\....\.........\verilog.asm
............\....\ddr_sdram_tb
............\....\............\_primary.dat
............\....\............\_primary.vhd
............\....\............\verilog.asm
............\....\mt46v4m16
............\....\.........\_primary.dat
............\....\.........\_primary.vhd
............\....\.........\verilog.asm
............\....\pll1
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\....\transcript
............\....\....\verilog.asm

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