I2C Inter Integrated Circuit Master Controller SourceCode

rd1005_i2c_master_controller\rd1005
............................\......\docs
............................\......\....\i2c_bus_specification.pdf
............................\......\....\rd1005.pdf
............................\......\....\rd1005_readme.txt
............................\......\....\revision_history.xlsx
............................\......\project
............................\......\.......\ecp3
............................\......\.......\....\verilog
............................\......\.......\....\.......\ecp3_verilog.ldf
............................\......\.......\....\.......\ecp3_verilog.lpf
............................\......\.......\....\.......\ecp3_verilog1.sty
............................\......\.......\....\vhdl
............................\......\.......\....\....\ecp3_vhdl.ldf
............................\......\.......\....\....\ecp3_vhdl.lpf
............................\......\.......\....\....\ecp3_vhdl1.sty
............................\......\.......\ecp5
............................\......\.......\....\verilog
............................\......\.......\....\.......\ecp5_verilog.ldf
............................\......\.......\....\.......\ecp5_verilog.lpf
............................\......\.......\....\.......\ecp5_verilog1.sty
............................\......\.......\....\vhdl
............................\......\.......\....\....\ecp5_vhdl.ldf
............................\......\.......\....\....\ecp5_vhdl.lpf
............................\......\.......\....\....\ecp5_vhdl1.sty
............................\......\.......\lptm
............................\......\.......\....\verilog
............................\......\.......\....\.......\lptm_verilog.ldf
............................\......\.......\....\.......\lptm_verilog.lpf
............................\......\.......\....\.......\lptm_verilog1.sty
............................\......\.......\....\vhdl
............................\......\.......\....\....\lptm_vhdl.ldf
............................\......\.......\....\....\lptm_vhdl.lpf
............................\......\.......\....\....\lptm_vhdl1.sty
............................\......\.......\xo
............................\......\.......\..\verilog
............................\......\.......\..\.......\xo_verilog.ldf
............................\......\.......\..\.......\xo_verilog.lpf
............................\......\.......\..\.......\xo_verilog1.sty
............................\......\.......\..\vhdl
............................\......\.......\..\....\xo_vhdl.ldf
............................\......\.......\..\....\xo_vhdl.lpf
............................\......\.......\..\....\xo_vhdl1.sty
............................\......\.......\xo2
............................\......\.......\...\verilog
............................\......\.......\...\.......\xo2_verilog.ldf
............................\......\.......\...\.......\xo2_verilog.lpf
............................\......\.......\...\.......\xo2_verilog1.sty
............................\......\.......\...\vhdl
............................\......\.......\...\....\xo2_vhdl.ldf
............................\......\.......\...\....\xo2_vhdl.lpf
............................\......\.......\...\....\xo2_vhdl1.sty
............................\......\.......\xo3l
............................\......\.......\....\verilog
............................\......\.......\....\.......\xo3l_verilog.ldf
............................\......\.......\....\.......\xo3l_verilog.lpf
............................\......\.......\....\.......\xo3l_verilog1.sty
............................\......\.......\....\vhdl
............................\......\.......\....\....\xo3l_vhdl.ldf
............................\......\.......\....\....\xo3l_vhdl.lpf
............................\......\.......\....\....\xo3l_vhdl1.sty
............................\......\.......\xp2
............................\......\.......\...\verilog
............................\......\.......\...\.......\xp2_verilog.ldf
............................\......\.......\...\.......\xp2_verilog.lpf

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