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  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-08-06
  • Size : 646kb
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  • Author :董***
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Digital clock digital display minutes and seconds, every hour the buzzer 2 seconds, curriculum design, verification by
Packet file list
(Preview for download)


timeclk\project\clock.asm.rpt
.......\.......\clock.done
.......\.......\clock.fit.rpt
.......\.......\clock.fit.smsg
.......\.......\clock.fit.summary
.......\.......\clock.flow.rpt
.......\.......\clock.map.rpt
.......\.......\clock.map.summary
.......\.......\clock.pin
.......\.......\clock.pof
.......\.......\clock.qpf
.......\.......\clock.qsf
.......\.......\clock.qws
.......\.......\clock.sim.rpt
.......\.......\clock.sof
.......\.......\clock.tan.rpt
.......\.......\clock.tan.summary
.......\.......\clock_driver.bsf
.......\.......\db\clock.asm.qmsg
.......\.......\..\clock.asm.rdb
.......\.......\..\clock.asm_labs.ddb
.......\.......\..\clock.cbx.xml
.......\.......\..\clock.cmp.bpm
.......\.......\..\clock.cmp.cdb
.......\.......\..\clock.cmp.ecobp
.......\.......\..\clock.cmp.hdb
.......\.......\..\clock.cmp.kpt
.......\.......\..\clock.cmp.logdb
.......\.......\..\clock.cmp.rdb
.......\.......\..\clock.cmp.tdb
.......\.......\..\clock.cmp0.ddb
.......\.......\..\clock.cmp2.ddb
.......\.......\..\clock.cmp_merge.kpt
.......\.......\..\clock.db_info
.......\.......\..\clock.eco.cdb
.......\.......\..\clock.eds_overflow
.......\.......\..\clock.fit.qmsg
.......\.......\..\clock.fnsim.cdb
.......\.......\..\clock.fnsim.hdb
.......\.......\..\clock.fnsim.qmsg
.......\.......\..\clock.hier_info
.......\.......\..\clock.hif
.......\.......\..\clock.lpc.html
.......\.......\..\clock.lpc.rdb
.......\.......\..\clock.lpc.txt
.......\.......\..\clock.map.bpm
.......\.......\..\clock.map.cdb
.......\.......\..\clock.map.ecobp
.......\.......\..\clock.map.hdb
.......\.......\..\clock.map.kpt
.......\.......\..\clock.map.logdb
.......\.......\..\clock.map.qmsg
.......\.......\..\clock.map_bb.cdb
.......\.......\..\clock.map_bb.hdb
.......\.......\..\clock.map_bb.logdb
.......\.......\..\clock.pre_map.cdb
.......\.......\..\clock.pre_map.hdb
.......\.......\..\clock.rtlv.hdb
.......\.......\..\clock.rtlv_sg.cdb
.......\.......\..\clock.rtlv_sg_swap.cdb
.......\.......\..\clock.sgdiff.cdb
.......\.......\..\clock.sgdiff.hdb
.......\.......\..\clock.sim.cvwf
.......\.......\..\clock.sim.hdb
.......\.......\..\clock.sim.qmsg
.......\.......\..\clock.sim.rdb
.......\.......\..\clock.simfam
.......\.......\..\clock.sld_design_entry.sci
.......\.......\..\clock.sld_design_entry_dsc.sci
.......\.......\..\clock.smart_action.txt
.......\.......\..\clock.syn_hier_info
.......\.......\..\clock.tan.qmsg
.......\.......\..\clock.tis_db_list.ddb
.......\.......\..\logic_util_heursitic.dat
.......\.......\..\mux_3nc.tdf
.......\.......\..\mux_joc.tdf
.......\.......\..\prev_cmp_clock.asm.qmsg
.......\.......\..\prev_cmp_clock.fit.qmsg
.......\.......\..\prev_cmp_clock.map.qmsg
.......\.......\..\prev_cmp_clock.qmsg
.......\.......\..\prev_cmp_clock.sim.qmsg
.......\.......\..\prev_cmp_clock.tan.qmsg
.......\.......\..\wed.wsf
.......\.......\incremental_db\compiled_partitions\clock.root_partition.cmp.cdb
.......\.......\..............\...................\clock.root_partition.cmp.dfp
.......\.......\..............\...................\clock.root_partition.cmp.hdb
.......\.......\..............\...................\clock.root_partition.cmp.kpt
.......\.......\..............\...................\clock.root_partition.cmp.logdb
.......\.......\..............\...................\clock.root_partition.cmp.rcfdb
.......\.......\..............\...................\clock.root_partition.cmp.re.rcfdb
.......\.......\..............\...................\clock.root_partition.map.cdb
.......\.......\..............\...................\clock.root_partition.map.dpi
.......\.......\..............\...................\clock.root_partition.map.hdb
.......\.......\..............\...................\clock.root_partition.map.kpt
.......\.......\..............\README
.......\.......\ScanLEDNum.bsf
.......\RTL\clock.vhd
.......\...\clock_driver.vhd
.......\...\clock_driver.vhd.bak
.......\...\clock_top.bdf
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