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sin_quartus9.0

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-08-10
  • Size : 4.04mb
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  • Author :俞****
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Introduction - If you have any usage issues, please Google them yourself
Implementation of Sine wave output with different phase.
Packet file list
(Preview for download)


sin2
....\clk_54k.v
....\db
....\..\altsyncram_au81.tdf
....\..\logic_util_heursitic.dat
....\..\prev_cmp_sin2.qmsg
....\..\sin2.amm.cdb
....\..\sin2.asm.qmsg
....\..\sin2.asm.rdb
....\..\sin2.asm_labs.ddb
....\..\sin2.cbx.xml
....\..\sin2.cmp.bpm
....\..\sin2.cmp.cdb
....\..\sin2.cmp.hdb
....\..\sin2.cmp.kpt
....\..\sin2.cmp.logdb
....\..\sin2.cmp.rdb
....\..\sin2.cmp_merge.kpt
....\..\sin2.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
....\..\sin2.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
....\..\sin2.db_info
....\..\sin2.eda.qmsg
....\..\sin2.fit.qmsg
....\..\sin2.hier_info
....\..\sin2.hif
....\..\sin2.idb.cdb
....\..\sin2.lpc.html
....\..\sin2.lpc.rdb
....\..\sin2.lpc.txt
....\..\sin2.map.bpm
....\..\sin2.map.cdb
....\..\sin2.map.hdb
....\..\sin2.map.kpt
....\..\sin2.map.logdb
....\..\sin2.map.qmsg
....\..\sin2.map_bb.cdb
....\..\sin2.map_bb.hdb
....\..\sin2.map_bb.logdb
....\..\sin2.pre_map.cdb
....\..\sin2.pre_map.hdb
....\..\sin2.rtlv.hdb
....\..\sin2.rtlv_sg.cdb
....\..\sin2.rtlv_sg_swap.cdb
....\..\sin2.sgdiff.cdb
....\..\sin2.sgdiff.hdb
....\..\sin2.sld_design_entry.sci
....\..\sin2.sld_design_entry_dsc.sci
....\..\sin2.smart_action.txt
....\..\sin2.sta.qmsg
....\..\sin2.sta.rdb
....\..\sin2.sta_cmp.8_slow_1200mv_85c.tdb
....\..\sin2.syn_hier_info
....\..\sin2.tiscmp.fastest_slow_1200mv_0c.ddb
....\..\sin2.tiscmp.fastest_slow_1200mv_85c.ddb
....\..\sin2.tiscmp.fast_1200mv_0c.ddb
....\..\sin2.tiscmp.slow_1200mv_0c.ddb
....\..\sin2.tiscmp.slow_1200mv_85c.ddb
....\..\sin2.tis_db_list.ddb
....\..\sin2.tmw_info
....\dizhihecheng.v
....\greybox_tmp
....\...........\cbx_args.txt
....\incremental_db
....\..............\compiled_partitions
....\..............\...................\sin2.db_info
....\..............\...................\sin2.root_partition.cmp.cdb
....\..............\...................\sin2.root_partition.cmp.dfp
....\..............\...................\sin2.root_partition.cmp.hdb
....\..............\...................\sin2.root_partition.cmp.kpt
....\..............\...................\sin2.root_partition.cmp.logdb
....\..............\...................\sin2.root_partition.cmp.rcfdb
....\..............\...................\sin2.root_partition.map.cdb
....\..............\...................\sin2.root_partition.map.dpi
....\..............\...................\sin2.root_partition.map.hbdb.cdb
....\..............\...................\sin2.root_partition.map.hbdb.hb_info
....\..............\...................\sin2.root_partition.map.hbdb.hdb
....\..............\...................\sin2.root_partition.map.hbdb.sig
....\..............\...................\sin2.root_partition.map.hdb
....\..............\...................\sin2.root_partition.map.kpt
....\..............\README
....\rom.bsf
....\rom.inc
....\rom.mif
....\rom.qip
....\rom.v
....\rom_bb.v
....\rom_inst.v
....\shujufenli.v
....\simulation
....\..........\modelsim
....\..........\........\modelsim.ini
....\..........\........\msim_transcript
....\..........\........\rom.mif
....\..........\........\rom.ver
....\..........\........\rtl_work
....\..........\........\........\clk_54k
....\..........\........\........\.......\_primary.dat
....\..........\........\........\.......\_primary.vhd
....\..........\........\........\dizhihecheng
....\..........\........\........\............\_primary.dat
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