Evaluation Kit for PCIe-sp605 xilinx verilog source (which has been commissioning)

xilinx评估板sp605的PCIe的verilog源程序(已经经过调试)\sp605_pcie_x1_gen1_canuse\iseconfig\s6_pcie_v2_3_verilog_example_project.projectmgr
....................................................\.........................\.........\xilinx_pcie_1_1_ep_s6.xreport
....................................................\.........................\par_usage_statistics.html
....................................................\.........................\readme.txt
....................................................\.........................\....y_for_download\make_spi_flash.bat
....................................................\.........................\..................\routed.bit
....................................................\.........................\..................\sp605_pcie_x1_gen1.cfi
....................................................\.........................\..................\sp605_pcie_x1_gen1.mcs
....................................................\.........................\..................\sp605_pcie_x1_gen1.prm
....................................................\.........................\..................\sp605_program_spi.cmd
....................................................\.........................\s6_pcie_v2_3\doc\ds801_s6_pcie.pdf
....................................................\.........................\............\...\s6_pcie_v2_3_vinfo.html
....................................................\.........................\............\...\ug672_S6_IntEndptBlock_PCIe.pdf
....................................................\.........................\............\example_design\pcie_app_s6.v
....................................................\.........................\............\..............\PIO.v
....................................................\.........................\............\..............\PIO_32_RX_ENGINE.v
....................................................\.........................\............\..............\PIO_32_TX_ENGINE.v
....................................................\.........................\............\..............\PIO_EP.v
....................................................\.........................\............\..............\PIO_EP_MEM.v
....................................................\.........................\............\..............\PIO_EP_MEM_ACCESS.v
....................................................\.........................\............\..............\PIO_TO_CTRL.v
....................................................\.........................\............\..............\xilinx_pcie_1_1_ep_s6.v
....................................................\.........................\............\..............\xilinx_pcie_1_lane_ep_xc6slx45t-fgg484-3.ucf
....................................................\.........................\............\implement\implement.bat
....................................................\.........................\............\.........\implement.log
....................................................\.........................\............\.........\implement.sh
....................................................\.........................\............\.........\results\mapped.mrp
....................................................\.........................\............\.........\.......\routed.bit
....................................................\.........................\............\.........\.......\routed.ncd
....................................................\.........................\............\.........\.......\routed.pad
....................................................\.........................\............\.........\.......\routed.par
....................................................\.........................\............\.........\.......\routed.unroutes
....................................................\.........................\............\.........\.......\routed.v
....................................................\.........................\............\.........\xilinx_pcie_1_1_ep

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