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  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-08-27
  • Size : 459kb
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  • Author :zuo***
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CPLD verilog program
Packet file list
(Preview for download)


共阴极\12\db\add_sub_eoh.tdf
......\..\..\add_sub_hoh.tdf
......\..\..\prev_cmp_RealTimeClock.asm.qmsg
......\..\..\prev_cmp_RealTimeClock.fit.qmsg
......\..\..\prev_cmp_RealTimeClock.map.qmsg
......\..\..\prev_cmp_RealTimeClock.qmsg
......\..\..\prev_cmp_RealTimeClock.tan.qmsg
......\..\..\RealTimeClock.asm.qmsg
......\..\..\RealTimeClock.cbx.xml
......\..\..\RealTimeClock.cmp.cdb
......\..\..\RealTimeClock.cmp.hdb
......\..\..\RealTimeClock.cmp.logdb
......\..\..\RealTimeClock.cmp.rdb
......\..\..\RealTimeClock.cmp.tdb
......\..\..\RealTimeClock.cmp0.ddb
......\..\..\RealTimeClock.db_info
......\..\..\RealTimeClock.eco.cdb
......\..\..\RealTimeClock.fit.qmsg
......\..\..\RealTimeClock.hier_info
......\..\..\RealTimeClock.hif
......\..\..\RealTimeClock.lpc.html
......\..\..\RealTimeClock.lpc.rdb
......\..\..\RealTimeClock.lpc.txt
......\..\..\RealTimeClock.map.cdb
......\..\..\RealTimeClock.map.hdb
......\..\..\RealTimeClock.map.logdb
......\..\..\RealTimeClock.map.qmsg
......\..\..\RealTimeClock.pre_map.cdb
......\..\..\RealTimeClock.pre_map.hdb
......\..\..\RealTimeClock.rtlv.hdb
......\..\..\RealTimeClock.rtlv_sg.cdb
......\..\..\RealTimeClock.rtlv_sg_swap.cdb
......\..\..\RealTimeClock.sgdiff.cdb
......\..\..\RealTimeClock.sgdiff.hdb
......\..\..\RealTimeClock.sld_design_entry.sci
......\..\..\RealTimeClock.sld_design_entry_dsc.sci
......\..\..\RealTimeClock.syn_hier_info
......\..\..\RealTimeClock.tan.qmsg
......\..\..\RealTimeClock.tis_db_list.ddb
......\..\..\RealTimeClock.tmw_info
......\..\incremental_db\compiled_partitions\RealTimeClock.root_partition.map.kpt
......\..\..............\README
......\..\key5.vhd
......\..\RealTimeClock.asm.rpt
......\..\RealTimeClock.cdf
......\..\RealTimeClock.done
......\..\RealTimeClock.dpf
......\..\RealTimeClock.fit.rpt
......\..\RealTimeClock.fit.summary
......\..\RealTimeClock.flow.rpt
......\..\RealTimeClock.map.rpt
......\..\RealTimeClock.map.summary
......\..\RealTimeClock.pin
......\..\RealTimeClock.pof
......\..\RealTimeClock.qpf
......\..\RealTimeClock.qsf
......\..\RealTimeClock.qws
......\..\RealTimeClock.tan.rpt
......\..\RealTimeClock.tan.summary
......\..\RealTimeClock.vhd
......\..\RealTimeClock.vhd.bak
......\scanled\db\add_sub_hoh.tdf
......\.......\..\prev_cmp_ScanLED.asm.qmsg
......\.......\..\prev_cmp_ScanLED.fit.qmsg
......\.......\..\prev_cmp_ScanLED.map.qmsg
......\.......\..\prev_cmp_ScanLED.qmsg
......\.......\..\prev_cmp_ScanLED.tan.qmsg
......\.......\..\ScanLED.db_info
......\.......\..\ScanLED.eco.cdb
......\.......\..\ScanLED.sld_design_entry.sci
......\.......\incremental_db\compiled_partitions\ScanLED.root_partition.map.kpt
......\.......\..............\README
......\.......\ScanLED.asm.rpt
......\.......\ScanLED.cdf
......\.......\ScanLED.done
......\.......\ScanLED.dpf
......\.......\ScanLED.fit.rpt
......\.......\ScanLED.fit.summary
......\.......\ScanLED.flow.rpt
......\.......\ScanLED.map.rpt
......\.......\ScanLED.map.summary
......\.......\ScanLED.pin
......\.......\ScanLED.pof
......\.......\ScanLED.qpf
......\.......\ScanLED.qsf
......\.......\ScanLED.qws
......\.......\ScanLED.tan.rpt
......\.......\ScanLED.tan.summary
......\.......\ScanLED.vhd
......\.......\ScanLED.vhd.bak
......\.......\ScanLED_assignment_defaults.qdf
......\12\incremental_db\compiled_partitions
......\scanled\incremental_db\compiled_partitions
......\12\db
......\..\incremental_db
......\scanled\db
......\.......\incremental_db
......\12
......\scanled
共阴极
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