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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-09-05
  • Size : 613kb
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  • Author :Je***
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Introduction - If you have any usage issues, please Google them yourself
It is a type of RISC processor..it is easily reconfigurable and virtualizable.it is implemented on FPGA
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ecpu\trunk\setup.sh
....\.....\components\svn-commit.tmp
....\.....\..........\adder\alu_adder.v
....\.....\..........\.lu\README
....\.....\..........\...\setup.sh
....\.....\..........\...\rtl\verilog\alu.v
....\.....\..........\...\...\.......\alu_barrel_shifter.v
....\.....\..........\...\...\.......\alu_controller.v
....\.....\..........\...\...\.......\alu_controller.vh
....\.....\..........\...\...\.......\alu_datapath.v
....\.....\..........\...\...\.......\alu_datapath.working_nosynth.v
....\.....\..........\...\...\.......\veriwell.key
....\.....\..........\...\...\.......\veriwell.log
....\.....\..........\...\...\.hdl\alu.vhd
....\.....\..........\...\...\....\alu_adder.vhd
....\.....\..........\...\...\....\alu_analog_cadence_tb.vhd
....\.....\..........\...\...\....\alu_analog_tb.vhd
....\.....\..........\...\...\....\alu_barrel_shifter.vhd
....\.....\..........\...\...\....\alu_barrel_shifter_tb.vhd
....\.....\..........\...\...\....\alu_controller.vhd
....\.....\..........\...\...\....\alu_datapath.vhd
....\.....\..........\...\...\....\alu_from_net.vhd
....\.....\..........\...\...\....\alu_stimulus.vhd
....\.....\..........\...\...\....\alu_tb.vhd
....\.....\..........\...\...\....\alu_test.txt
....\.....\..........\...\...\....\compile.simili.files
....\.....\..........\...\...\....\compile_alu.simili.files
....\.....\..........\...\...\....\do_all_simili
....\.....\..........\...\...\....\runit
....\.....\..........\...\scripts\conv_fsm.pl
....\.....\..........\...\.im\alu_tb.vcd
....\.....\..........\...\...\alu_test.txt
....\.....\..........\...\...\log
....\.....\..........\...\...\runit
....\.....\..........\...\...\run_alu
....\.....\..........\...\.ynth\check_for_synth
....\.....\..........\...\.....\veriwell.key
....\.....\..........\...\.....\veriwell.log
....\.....\..........\...\..stemc\alu_tb.v
....\.....\..........\...\.......\gen_systemc.sh
....\.....\..........\...\.......\log
....\.....\..........\...\.......\bak\Makefile
....\.....\..........\...\.......\...\verilated.cpp
....\.....\..........\...\.......\obj_dir\Makefile
....\.....\..........\...\.......\.......\run.x
....\.....\..........\...\.......\.......\sc_main.cpp
....\.....\..........\...\.......\.......\tracefile.vcd
....\.....\..........\...\.......\.......\Valu_tb.cpp
....\.....\..........\...\.......\.......\Valu_tb.h
....\.....\..........\...\.......\.......\Valu_tb.mk
....\.....\..........\...\.......\.......\Valu_tb_alu_tb.cpp
....\.....\..........\...\.......\.......\Valu_tb_alu_tb.h
....\.....\..........\...\.......\.......\Valu_tb_classes.mk
....\.....\..........\...\.......\.......\Valu_tb__ALLcls.cpp
....\.....\..........\...\.......\.......\Valu_tb__ALLcls.d
....\.....\..........\...\.......\.......\Valu_tb__ALLsup.cpp
....\.....\..........\...\.......\.......\Valu_tb__ALLsup.d
....\.....\..........\...\.......\.......\Valu_tb__Inlines.h
....\.....\..........\...\.......\.......\Valu_tb__Syms.cpp
....\.....\..........\...\.......\.......\Valu_tb__Syms.h
....\.....\..........\...\.......\.......\Valu_tb__ver.d
....\.....\..........\...\.......\.......\Valu_tb__verFiles.dat
....\.....\..........\...\.......\.......\verilated.cpp
....\.....\..........\...\.......\.......\verilog_sc.h
....\.....\..........\...\tb\alu_tb.v
....\.....\..........\barrel_shifter\simple\barrel_shifter_simple.temp.v
....\.....\..........\..............\......\barrel_shifter_simple.v
....\.....\..........\..............\......\barrel_shifter_simple.working_nosynth.v
....\.....\..........\ram\ram.v
....\.....\..........\...\ram_mk_x_n.v
....\.....\..........\.om\rom.v
....\.....\lib\dff.v
....\.....\...\mux2to1_case.v
....\.....\rtl\verilog\ecpu.v
....\.....\...\.......\ecpu_core.vh
....\.....\...\.......\ecpu_core_controller.v
....\.....\...\.......\ecpu_core_datapath.v
....\.....\...\.......\ecpu_core_generic.v
....\.....\scratch\a.out
....\.....\.......\main.c
....\.....\.im\ecpu_tb.vcd
....\.....\...\log
....\.....\...\rom_data.vh
....\.....\...\rtl.list
....\.....\...\runit.sh
....\.....\...\run_ecpu
....\.....\...\tb.list
....\.....
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