Hot Search : Source embeded web remote control p2p game More...
Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog

Display_7seg

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2015-09-09
  • Size : 475kb
  • Downloaded :0次
  • Author :罗***
  • About : Nobody
  • PS : If download it fails, try it again. Download again for free!
Introduction - If you have any usage issues, please Google them yourself
Basys 3 development board entry test, key control of the 7 section of the digital tube display test.
Packet file list
(Preview for download)


Display_7seg\Display_7seg.cache\wt\java_command_handlers.wdf
............\..................\..\synthesis.wdf
............\..................\..\synthesis_details.wdf
............\..................\..\webtalk_pa.xml
............\..................\..\xsim.wdf
............\.............hw\Display_7seg.lpr
............\...............\webtalk\.xsim_webtallk.info
............\...............\.......\usage_statistics_ext_labtool.wdm
............\.............runs\.jobs\vrs_config_1.xml
............\.................\.....\vrs_config_10.xml
............\.................\.....\vrs_config_11.xml
............\.................\.....\vrs_config_2.xml
............\.................\.....\vrs_config_3.xml
............\.................\.....\vrs_config_4.xml
............\.................\.....\vrs_config_5.xml
............\.................\.....\vrs_config_6.xml
............\.................\.....\vrs_config_7.xml
............\.................\.....\vrs_config_8.xml
............\.................\.....\vrs_config_9.xml
............\.................\impl_1\.init_design.begin.rst
............\.................\......\.init_design.end.rst
............\.................\......\.opt_design.begin.rst
............\.................\......\.opt_design.end.rst
............\.................\......\.place_design.begin.rst
............\.................\......\.place_design.end.rst
............\.................\......\.route_design.begin.rst
............\.................\......\.route_design.end.rst
............\.................\......\.vivado.begin.rst
............\.................\......\.vivado.end.rst
............\.................\......\.Vivado_Implementation.queue.rst
............\.................\......\.write_bitstream.begin.rst
............\.................\......\.write_bitstream.end.rst
............\.................\......\display_7seg.bit
............\.................\......\display_7seg.tcl
............\.................\......\display_7seg.vdi
............\.................\......\display_7seg_11708.backup.vdi
............\.................\......\display_7seg_7808.backup.vdi
............\.................\......\display_7seg_clock_utilization_placed.rpt
............\.................\......\display_7seg_control_sets_placed.rpt
............\.................\......\display_7seg_drc_opted.rpt
............\.................\......\display_7seg_drc_routed.pb
............\.................\......\display_7seg_drc_routed.rpt
............\.................\......\display_7seg_io_placed.rpt
............\.................\......\display_7seg_opt.dcp
............\.................\......\display_7seg_placed.dcp
............\.................\......\display_7seg_power_routed.rpt
............\.................\......\display_7seg_power_summary_routed.pb
............\.................\......\display_7seg_routed.dcp
............\.................\......\display_7seg_route_status.pb
............\.................\......\display_7seg_route_status.rpt
............\.................\......\display_7seg_timing_summary_routed.rpt
............\.................\......\display_7seg_timing_summary_routed.rpx
............\.................\......\display_7seg_utilization_placed.pb
............\.................\......\display_7seg_utilization_placed.rpt
............\.................\......\gen_run.xml
............\.................\......\htr.txt
............\.................\......\init_design.pb
............\.................\......\ISEWrap.js
............\.................\......\ISEWrap.sh
............\.................\......\opt_design.pb
............\.................\......\place_design.pb
............\.................\......\project.wdf
............\.................\......\route_design.pb
............\.................\......\rundef.js
............\.................\......\runme.bat
............\.................\......\runme.log
............\.................\......\runme.sh
............\.................\......\usage_statistics_webtalk.html
............\.................\......\usage_statistics_webtalk.xml
..........
Related instructions
  • We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
  • The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
  • Please use Winrar for decompression tools
  • If download fail, Try it againg or Feedback to us.
  • If downloaded content did not match the introduction, Feedback to us,Confirm and will be refund.
  • Before downloading, you can inquire through the uploaded person information

Nothing.

Post Comment
*Quick comment Recommend Not bad Password Unclear description Not source
Lost files Unable to decompress Bad
*Content :
*Captcha :
CodeBus is the largest source code store in internet!
Contact us :
1999-2046 CodeBus All Rights Reserved.