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latticeECP3-serdes-test-code

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-09-13
  • Size : 5.17mb
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lattice ECP3 series high speed serdes test code
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latticeECP3 serdes test code\for_alex\.floorplanner.ini
............................\........\.run_manager.ini
............................\........\.setting.ini
............................\........\.spreadsheet_view.ini
............................\........\.spread_sheet.ini
............................\........\._test16.clpf
............................\........\AA.rvl
............................\........\AA.rvs
............................\........\ddr2.ipx
............................\........\ddr2.lpc
............................\........\ddr2.ngo
............................\........\ddr2_bb.v
............................\........\ddr2_beh.v
............................\........\ddr2_filelist.log
............................\........\ddr2_gen.log
............................\........\ddr2_generate.log
............................\........\ddr2_inst.v
............................\........\ddr3t_generate.log
............................\........\..._p_eval\eval_sim_readme.txt
............................\........\..........\models\ecp3\ddr_data_io.v
............................\........\..........\......\....\ddr_dm_io.v
............................\........\..........\......\....\ddr_dqs_io.v
............................\........\..........\......\....\ddr_sdram_mem_io_top.v
............................\........\..........\......\....\DQSBUFF.v
............................\........\..........\......\....\pio_dvalid_gen.v
............................\........\..........\......\....\pmi_distributed_dpram.v
............................\........\..........\......\....\pmi_pll_fp.v
............................\........\..........\......\mem\ddr2.v
............................\........\..........\......\...\ddr2_db_width_32.v
............................\........\..........\......\...\ddr2_parameters.vh
............................\........\..........\readme.htm
............................\........\..........\testbench\tests\ecp3\cmd_gen.v
............................\........\..........\.........\.....\....\tb_config_params.v
............................\........\..........\.........\.....\....\testcase.v
............................\........\..........\.........\.op\ecp3\monitor.v
............................\........\..........\.........\...\....\odt_watchdog.v
............................\........\..........\.........\...\....\test_mem_ctrl.v
............................\........\ddr_sdram_mem_params.v
............................\........\dummy_sym.sort
............................\........\generate_core.tcl
............................\........\IP\dummy_sym.sort
............................\........\..\fifo_18x.ipx
............................\........\..\fifo_18x.lpc
............................\........\..\fifo_18x.naf
............................\........\..\fifo_18x.sort
............................\........\..\fifo_18x.srp
............................\........\..\fifo_18x.sym
............................\........\..\fifo_18x.v
............................\........\..\fifo_18x_generate.log
............................\........\..\fifo_18x_tmpl.v
............................\........\..\msg_file.log
............................\........\..\serdes_pcs.ipx
............................\........\..\serdes_pcs.lpc
............................\........\..\serdes_pcs.naf
............................\........\..\serdes_pcs.pp
............................\........\..\serdes_pcs.readme
............................\........\..\serdes_pcs.sort
............................\........\..\serdes_pcs.sym
............................\........\..\serdes_pcs.tft
............................\........\..\serdes_pcs.txt
............................\........\..\serdes_pcs.v
............................\........\..\serdes_pcs.v.bak
............................\........\..\serdes_pcsrx_reset_sm.naf
............................\........\..\serdes_pcstx_reset_sm.naf
............................\........\..\serdes_pcs_generate.log
............................\........\..\tb_fifo_18x_tmpl.v
............................\........\reportvi
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