SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development

SRIO phy code\pcs code\srio_pcs_code\core\wl_fifo.v
.............\........\.............\....\wl_fpga_afifo_192x16.v
.............\........\.............\rtl\srio_pcs.v
.............\........\.............\...\srio_pcs_descram.v
.............\........\.............\...\srio_pcs_descram_lane.v
.............\........\.............\...\srio_pcs_descram_scram.v
.............\........\.............\...\srio_pcs_descram_seed_adstract.v
.............\........\.............\...\srio_pcs_descram_seq_gen.v
.............\........\.............\...\srio_pcs_descram_sync_check.v
.............\........\.............\...\srio_pcs_descram_xor.v
.............\........\.............\...\srio_pcs_d_idle_gen.v
.............\........\.............\...\srio_pcs_d_idle_gen_ctrl.v
.............\........\.............\...\srio_pcs_d_idle_gen_lane.v
.............\........\.............\...\srio_pcs_d_scram.v
.............\........\.............\...\srio_pcs_d_scram_ctrl.v
.............\........\.............\...\srio_pcs_d_scram_lane.v
.............\........\.............\...\srio_pcs_d_scram_seq.v
.............\........\.............\...\srio_pcs_gi_rx.v
.............\........\.............\...\srio_pcs_gi_rx_bw.v
.............\........\.............\...\srio_pcs_gi_rx_destripe.v
.............\........\.............\...\srio_pcs_gi_rx_fifo.v
.............\........\.............\...\srio_pcs_gi_tx.v
.............\........\.............\...\srio_pcs_gi_tx_bw.v
.............\........\.............\...\srio_pcs_gi_tx_ccs_index.v
.............\........\.............\...\srio_pcs_gi_tx_fifo.v
.............\........\.............\...\srio_pcs_gi_tx_flow_fifo.v
.............\........\.............\...\srio_pcs_gi_tx_stripe.v
.............\........\.............\...\srio_pcs_init.v
.............\........\.............\...\srio_pcs_init_1x_mode_detect.v
.............\........\.............\...\srio_pcs_init_1x_mode_detect_sub.v
.............\........\.............\...\srio_pcs_init_deskew.v
.............\........\.............\...\srio_pcs_init_deskew_2x.v
.............\........\.............\...\srio_pcs_init_deskew_4x.v
.............\........\.............\...\srio_pcs_init_deskew_adj.v
.............\........\.............\...\srio_pcs_init_deskew_cal.v
.............\........\.............\...\srio_pcs_init_idle_detect.v
.............\........\.............\...\srio_pcs_init_lane_align.v
.............\........\.............\...\srio_pcs_init_lane_align_state.v
.............\........\.............\...\srio_pcs_init_lane_sync.v
.............\........\.............\...\srio_pcs_init_lane_sync_lane.v
.............\........\.............\...\srio_pcs_init_mode_sel.v
.............\........\.............\...\srio_pcs_status.v
.............\receive and master\ctrl_pack_proc_4x.v
.............\..................\ctrl_sym_proc_2x_4x.v
.............\..................\pack_proc_2x.v
.............\..................\srio_cs_crc13.v
.............\..................\srio_cs_crc5.v
.............\..................\srio_data_crc16.v
.............\..................\srio_phy_buf_ctrl.v
.............\..................\srio_phy_fifo_15x64.v
.............\..................\srio_phy_fifo_6x64.v
.............\..................\srio_phy_master_control.v
.............\..................\srio_phy_ram_64x4096.v
.............\..................\srio_phy_reg.v
.............\..................\srio_phy_rx.v
.............\srio_phy_top.v
.............\transmit code\contrl_err_detect.v
.............\.............\data_128_to_64_switch.v
.............\.............\data_logic_analys.v
.............\.............\ipcore\ram_128_to_64\greybox_tmp\cbx_args.txt
.............\.............\......\.............\ram_128_to_64.qip
.............\.............\......\.............\ram_128_to_64.v
.............\.............\......\.............\ram_128_to_64_bb.v
.............\.............\......\....dat_fifo2240x64\greybox_tmp\cbx_args.txt
.............\.............\......\...................\ram_128_to_64_bb.qip
.............\.............\......\...................\ram_dat_fifo_2240x

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