Basic vhdl code for and gate logic.

Proj_AND_V1\AND2.bld
...........\AND2.cmd_log
...........\AND2.lso
...........\AND2.ncd
...........\AND2.ngc
...........\AND2.ngd
...........\AND2.ngr
...........\AND2.par
...........\AND2.pcf
...........\AND2.prj
...........\AND2.stx
...........\AND2.syr
...........\AND2.tfi
...........\AND2.twr
...........\AND2.twx
...........\AND2.unroutes
...........\AND2.vhd
...........\AND2.xst
...........\AND2_envsettings.html
...........\AND2_fpga_editor.log
...........\AND2_guide.ncd
...........\AND2_map.map
...........\AND2_map.mrp
...........\AND2_map.ncd
...........\AND2_map.ngm
...........\AND2_pad.csv
...........\AND2_pad.txt
...........\AND2_summary.html
...........\AND2_xst.xrpt
...........\deco_7seg.vhd
...........\Div_Clk_26.vhd
...........\Nexys3_Master.ucf
...........\pa.fromNetlist.tcl
...........\par_usage_statistics.html
...........\pepExtractor.prj
...........\planAhead.ngc2edif.log
...........\Proj_AND_V1.gise
...........\Proj_AND_V1.xise
...........\top_teste_and2_v1.bgn
...........\top_teste_and2_v1.bit
...........\Top_Teste_And2_V1.bld
...........\Top_Teste_And2_V1.cmd_log
...........\top_teste_and2_v1.drc
...........\Top_Teste_And2_V1.lso
...........\Top_Teste_And2_V1.ncd
...........\Top_Teste_And2_V1.ngc
...........\Top_Teste_And2_V1.ngd
...........\Top_Teste_And2_V1.ngr
...........\Top_Teste_And2_V1.pad
...........\Top_Teste_And2_V1.par
...........\Top_Teste_And2_V1.pcf
...........\Top_Teste_And2_V1.prj
...........\Top_Teste_And2_V1.ptwx
...........\Top_Teste_And2_V1.spl
...........\Top_Teste_And2_V1.stx
...........\Top_Teste_And2_V1.sym
...........\Top_Teste_And2_V1.syr
...........\Top_Teste_And2_V1.twr
...........\Top_Teste_And2_V1.twx
...........\Top_Teste_And2_V1.ucf
...........\Top_Teste_And2_V1.unroutes
...........\Top_Teste_And2_V1.ut
...........\Top_Teste_And2_V1.vhd
...........\Top_Teste_And2_V1.xpi
...........\Top_Teste_And2_V1.xst
...........\Top_Teste_And2_V1_bitgen.xwbt
...........\Top_Teste_And2_V1_envsettings.html
...........\Top_Teste_And2_V1_fpga_editor.log
...........\Top_Teste_And2_V1_guide.ncd
...........\Top_Teste_And2_V1_map.map
...........\Top_Teste_And2_V1_map.mrp
...........\Top_Teste_And2_V1_map.ncd
...........\Top_Teste_And2_V1_map.ngm
...........\Top_Teste_And2_V1_map.xrpt
...........\Top_Teste_And2_V1_ngdbuild.xrpt
...........\Top_Teste_And2_V1_pad.csv
...........\Top_Teste_And2_V1_pad.txt
...........\Top_Teste_And2_V1_par.xrpt
...........\Top_Teste_And2_V1_preroute.twr
...........\Top_Teste_And2_V1_preroute.twx
...........\Top_Teste_And2_V1_summary.html
...........\Top_Teste_And2_V1_summary.xml
...........\Top_Teste_And2_V1_usage.xml
...........\Top_Teste_And2_V1_xst.xrpt
...........\usage_statistics_webtalk.html
...........\webtalk.log
...........\webtalk_pn.xml
...........\iseconfig\AND2.xreport
...........\.........\Proj_AND_V1.projectmgr
...........\.........\Top_Teste_And2_V1.xreport
...........\planAhead_run_1\planAhead.jou
...........\...............\planAhead.log
...........\...............\planAhead_run.log
...........\...............\Proj_AND_V1.ppr
...........\...............\............data\cache\Top_Teste_And2_V1_ngc_83d685c.edif
...........\...............\................\.onstrs_1\fileset.xml
...........\...............\................\runs\impl_1.psg
...........\...............\................\....\runs.xml
...........\...............\................\sources_1\fileset.xml
...........\...............\................\wt\project.wpc

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