actel VERILOG BLDC control of the use of actel FPGA

Application Note Disclaimer.doc
bldc_ip\bldc_ip_libero_project.prj
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\........\impl1
.......\........\.....\designer.log
.......\........\.....\simulation
.......\........\.....\top_bldc_ip.adb
.......\........\.....\top_bldc_ip.dtf
.......\........\.....\...............\verify.log
.......\........\.....\top_bldc_ip.ide_des
.......\........\.....\top_bldc_ip.stp
.......\........\.....\top_bldc_ip.tcl
.......\hdl
.......\...\baud_clk_gen.v
.......\...\bd_bl_speedcontrol.v
.......\...\bdbl_driver.v
.......\...\bldc_ip.v
.......\...\clk_by_2.v
.......\...\clk_gen.v
.......\...\clkdiv_20M_to_10M.v
.......\...\debounce.v
.......\...\debounce_blk.v
.......\...\div_by_16.v
.......\...\divideby5.v
.......\...\global.v
.......\...\mux_hw_sw.v
.......\...\PLL20_to_10.v
.......\...\pwm_gen_bdbl.v
.......\...\recv_control.v
.......\...\serial.v
.......\...\top_bldc.v
.......\...\top_bldc_ip.v
.......\...\top_serial.v
.......\...\xmit_control.v
.......\phy_synthesis
.......\Readme_bldc_ip_project.txt
.......\simulation
.......\..........\modelsim.ini
.......\..........\modelsim.ini.sav
.......\..........\modelsim.log
.......\..........\presynth
.......\..........\........\_info
.......\..........\........\_temp
.......\..........\........\baud_clk_gen
.......\..........\........\............\_primary.dat
.......\..........\........\............\_primary.dbs
.......\..........\........\............\_primary.vhd
.......\..........\........\............\verilog.psm
.......\..........\........\bd_bl_speedcontrol
.......\..........\........\..................\_primary.dat
.......\..........\........\..................\_primary.dbs
.......\..........\........\..................\_primary.vhd
.......\..........\........\..................\verilog.psm
.......\..........\........\bdbl_driver
.......\..........\........\...........\_primary.dat
.......\..........\........\...........\_primary.dbs
.......\..........\........\...........\_primary.vhd
.......\..........\........\...........\verilog.psm
.......\..........\........\bldc_ip
.......\..........\........\.......\_primary.dat
.......\..........\........\.......\_primary.dbs
.......\..........\........\.......\_primary.vhd
.......\..........\........\.......\verilog.psm
.......\..........\........\clk_by_2
.......\..........\........\........\_primary.dat
.......\..........\........\........\_primary.dbs
.......\..........\........\........\_primary.vhd
.......\..........\........\........\verilog.psm
.......\..........\........\clk_gen
.......\..........\........\.......\_primary.dat
.......\..........\........\.......\_primary.dbs
.......\..........\........\.......\_primary.vhd
.......\..........\........\.......\verilog.psm
.......\..........\........\clkdiv_20@m_to_10@m
.......\..........\........\...................\_primary.dat
.......\..........\........\...................\_primary.dbs
.......\..........\........\...................\_primary.vhd
.......\..........\........\...................\verilog.psm
.......\..........\........\debounce
.......\..........\........\........\_primary.dat
.......\..........\........\........\_primary.dbs
.......\..........\........\........\_primary.vhd
.......\..........\........\........\verilog.psm
.......\..........\........\debounce_blk
.......\..........\........\............\_primary.dat
.......\..........\........\............\_primary.dbs
.......\..........\........\............\_primary.vhd
.......\..........\........\............\verilog.psm
.......\..........\........\div_by_16
.......\..........\........\.........\_primary.dat
.......\..........\........\.........\_primary.dbs
.......\..........\........\.........\_primary.vhd
.......\..........\........\.........\verilog.psm
.......\..........\........\divideby5
.......\..........\........\.........\_primary.dat
.......\..........\........\.........\_primary.dbs
.......\..........\........\.........\_primary.vhd

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