FPGA design is based on simple traffic light, which is designed with two directions of light, respectively, three red, green and yellow lights, traffic in both directions alternately

lyl交通灯
.........\control1
.........\........\db
.........\........\..\fangxiang1.asm.qmsg
.........\........\..\fangxiang1.cbx.xml
.........\........\..\fangxiang1.cmp.cdb
.........\........\..\fangxiang1.cmp.hdb
.........\........\..\fangxiang1.cmp.kpt
.........\........\..\fangxiang1.cmp.logdb
.........\........\..\fangxiang1.cmp.rdb
.........\........\..\fangxiang1.cmp.tdb
.........\........\..\fangxiang1.cmp0.ddb
.........\........\..\fangxiang1.dbp
.........\........\..\fangxiang1.db_info
.........\........\..\fangxiang1.eco.cdb
.........\........\..\fangxiang1.eds_overflow
.........\........\..\fangxiang1.fit.qmsg
.........\........\..\fangxiang1.hier_info
.........\........\..\fangxiang1.hif
.........\........\..\fangxiang1.map.cdb
.........\........\..\fangxiang1.map.hdb
.........\........\..\fangxiang1.map.logdb
.........\........\..\fangxiang1.map.qmsg
.........\........\..\fangxiang1.pre_map.cdb
.........\........\..\fangxiang1.pre_map.hdb
.........\........\..\fangxiang1.psp
.........\........\..\fangxiang1.pss
.........\........\..\fangxiang1.rtlv.hdb
.........\........\..\fangxiang1.rtlv_sg.cdb
.........\........\..\fangxiang1.rtlv_sg_swap.cdb
.........\........\..\fangxiang1.sgdiff.cdb
.........\........\..\fangxiang1.sgdiff.hdb
.........\........\..\fangxiang1.signalprobe.cdb
.........\........\..\fangxiang1.sim.hdb
.........\........\..\fangxiang1.sim.qmsg
.........\........\..\fangxiang1.sim.rdb
.........\........\..\fangxiang1.sim.vwf
.........\........\..\fangxiang1.sld_design_entry.sci
.........\........\..\fangxiang1.sld_design_entry_dsc.sci
.........\........\..\fangxiang1.syn_hier_info
.........\........\..\fangxiang1.tan.qmsg
.........\........\..\wed.zsf
.........\........\fangxiang1.asm.rpt
.........\........\fangxiang1.done
.........\........\fangxiang1.fit.rpt
.........\........\fangxiang1.fit.smsg
.........\........\fangxiang1.fit.summary
.........\........\fangxiang1.flow.rpt
.........\........\fangxiang1.map.rpt
.........\........\fangxiang1.map.summary
.........\........\fangxiang1.pin
.........\........\fangxiang1.pof
.........\........\fangxiang1.qpf
.........\........\fangxiang1.qsf
.........\........\fangxiang1.qws
.........\........\fangxiang1.sim.rpt
.........\........\fangxiang1.sof
.........\........\fangxiang1.tan.rpt
.........\........\fangxiang1.tan.summary
.........\........\fangxiang1.vhd
.........\........\fangxiang1.vwf
.........\........\fangxiang1_assignment_defaults.qdf
.........\control2
.........\........\db
.........\........\..\fangxiang2.db_info
.........\........\..\fangxiang2.eco.cdb
.........\........\..\fangxiang2.sld_design_entry.sci
.........\........\..\wed.zsf
.........\........\fangxiang2.asm.rpt
.........\........\fangxiang2.done
.........\........\fangxiang2.fit.rpt
.........\........\fangxiang2.fit.smsg
.........\........\fangxiang2.fit.summary
.........\........\fangxiang2.flow.rpt
.........\........\fangxiang2.map.rpt
.........\........\fangxiang2.map.summary
.........\........\fangxiang2.pin
.........\........\fangxiang2.pof
.........\........\fangxiang2.qpf
.........\........\fangxiang2.qsf
.........\........\fangxiang2.qws
.........\........\fangxiang2.sim.rpt
.........\........\fangxiang2.sof
.........\........\fangxiang2.tan.rpt
.........\........\fangxiang2.tan.summary
.........\........\fangxiang2.vhd
.........\........\fangxiang2.vwf
.........\........\fangxiang2_assignment_defaults.qdf
.........\dingceng
.........\........\db
.........\........\..\dingceng.asm.qmsg
.........\........\..\dingceng.cbx.xml
.........\........\..\dingceng.cmp.cdb
.........\........\..\dingceng.cmp.hdb
.........\........\..\dingceng.cmp.kpt
.........\........\..\dingceng.cmp.logdb
.........\........\..\dingceng.cmp.rdb
.........\........\..\dingceng.cmp.tdb
.........\........\..\dingceng.cmp0.ddb
.........\........\..\dingceng.dbp

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