FPGA (EP3 Series) any integer frequency VHDL program, modify the program can meet the requirements of n

test
....\CLK
....\clkdiv.asm.rpt
....\clkdiv.cdf
....\clkdiv.done
....\clkdiv.eda.rpt
....\clkdiv.fit.rpt
....\clkdiv.fit.smsg
....\clkdiv.fit.summary
....\clkdiv.flow.rpt
....\clkdiv.map.rpt
....\clkdiv.map.summary
....\clkdiv.pin
....\clkdiv.pof
....\clkdiv.qpf
....\clkdiv.qsf
....\clkdiv.qws
....\clkdiv.sdc
....\clkdiv.sof
....\clkdiv.sta.rpt
....\clkdiv.sta.summary
....\clkdiv.vhd
....\clkdiv.vhd.bak
....\clkdiv_assignment_defaults.qdf
....\CLK\clkdiv.asm.rpt
....\...\clkdiv.cdf
....\...\clkdiv.done
....\...\clkdiv.eda.rpt
....\...\clkdiv.fit.rpt
....\...\clkdiv.fit.smsg
....\...\clkdiv.fit.summary
....\...\clkdiv.flow.rpt
....\...\clkdiv.map.rpt
....\...\clkdiv.map.summary
....\...\clkdiv.pin
....\...\clkdiv.pof
....\...\clkdiv.qpf
....\...\clkdiv.qsf
....\...\clkdiv.sdc
....\...\clkdiv.sdc.bak
....\...\clkdiv.sof
....\...\clkdiv.sta.rpt
....\...\clkdiv.sta.summary
....\...\clkdiv.v
....\...\clkdiv.v.bak
....\...\clkdiv.vhd
....\...\clkdiv.vhd.bak
....\...\clkdiv_nativelink_simulation.rpt
....\...\db
....\...\..\clkdiv.amm.cdb
....\...\..\clkdiv.asm.qmsg
....\...\..\clkdiv.asm.rdb
....\...\..\clkdiv.asm_labs.ddb
....\...\..\clkdiv.cbx.xml
....\...\..\clkdiv.cmp.bpm
....\...\..\clkdiv.cmp.cdb
....\...\..\clkdiv.cmp.hdb
....\...\..\clkdiv.cmp.kpt
....\...\..\clkdiv.cmp.logdb
....\...\..\clkdiv.cmp.rdb
....\...\..\clkdiv.cmp_merge.kpt
....\...\..\clkdiv.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
....\...\..\clkdiv.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
....\...\..\clkdiv.db_info
....\...\..\clkdiv.eda.qmsg
....\...\..\clkdiv.fit.qmsg
....\...\..\clkdiv.hier_info
....\...\..\clkdiv.hif
....\...\..\clkdiv.idb.cdb
....\...\..\clkdiv.lpc.html
....\...\..\clkdiv.lpc.rdb
....\...\..\clkdiv.lpc.txt
....\...\..\clkdiv.map.bpm
....\...\..\clkdiv.map.cdb
....\...\..\clkdiv.map.hdb
....\...\..\clkdiv.map.kpt
....\...\..\clkdiv.map.logdb
....\...\..\clkdiv.map.qmsg
....\...\..\clkdiv.map_bb.cdb
....\...\..\clkdiv.map_bb.hdb
....\...\..\clkdiv.map_bb.logdb
....\...\..\clkdiv.pre_map.cdb
....\...\..\clkdiv.pre_map.hdb
....\...\..\clkdiv.rtlv.hdb
....\...\..\clkdiv.rtlv_sg.cdb
....\...\..\clkdiv.rtlv_sg_swap.cdb
....\...\..\clkdiv.sgdiff.cdb
....\...\..\clkdiv.sgdiff.hdb
....\...\..\clkdiv.sld_design_entry.sci
....\...\..\clkdiv.sld_design_entry_dsc.sci
....\...\..\clkdiv.smart_action.txt
....\...\..\clkdiv.sta.qmsg
....\...\..\clkdiv.sta.rdb
....\...\..\clkdiv.sta_cmp.8_slow_1200mv_85c.tdb
....\...\..\clkdiv.syn_hier_info
....\...\..\clkdiv.taw.rdb
....\...\..\clkdiv.tiscmp.fastest_slow_1200mv_0c.ddb
....\...\..\clkdiv.tiscmp.fastest_slow_1200mv_85c.ddb
....\...\..\clkdiv.tiscmp.fast_1200mv_0c.ddb
....\...\..\clkdiv.tiscmp.slow_1200mv_0c.ddb

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