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  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-11-02
  • Size : 4kb
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  • Author :刘****
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Introduction - If you have any usage issues, please Google them yourself
The input signal to achieve the 1.5 multiplier, input digital signal frequency range is 1050 ~ 1100Hz (not necessarily a 50 duty cycle square wave, and the input signal frequency may change slowly in 1050 ~ 1100Hz, frequency change rate is not higher than the less than 10Hz/s), the requirements of 50 duty cycle output signal, and the frequency is 1.5 times the input voltage, and continuously track the input frequency, and phase change.
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DPLL\Ctrl.vhd
....\dpll_tb.ucf
....\dpll_tb.vhd
DPLL
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