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Screen-saver

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-11-02
  • Size : 5kb
  • Downloaded :0次
  • Author :刘****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Design a screen saver, its compilation, simulation, download. Screen Savers specific requirements are as follows: 1. Use the attached ISE CORE Generator block RAM/ROM data stored in an image, this module as part of a screen saver, the screen saver storage used in the image. 2. When you start the program or press btn [3], the image is displayed as an image in the upper left corner pixel initial position to its initial position (C1, R1) at, (C1, R1). Here, we set the initial position of the upper left corner is the coordinate (0,0). 3. Press btn [0], the image generation dynamic effect in accordance with the set mode. Our experimental design is pressed btn [0] picture begins to move, according to the law of reflection of light reflected encounters boundaries. 4. experiment with pictures of students of their own choice, here, we have chosen to operate the following picture. 5. OPTIONAL function: join the action selection, use DIP switch sw or trigger dynamic effects key btn enter the numb
Packet file list
(Preview for download)


Screen saver\address.vhd
............\clock.vhd
............\pixelcnt.vhd
............\readme.txt
............\usermode.vhd
............\vgacolor.vhd
............\vgasig.vhd
Screen saver
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