A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.

DDR2_CONTROLLER-master
......................\CLOCK.sv
......................\DDR2SIM.sv
......................\DDR2SIM.vhd
......................\DDR2_M.v
......................\DDR2_PARAMETERS.vh
......................\DDR_CONTROL.vhd
......................\LICENSE
......................\README.md
......................\Testbench_Design.vsdx
......................\cmp.py
......................\problem.txt
......................\text.py
......................\textfile_r.dat
......................\textfile_st.dat
......................\textfile_w.dat

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