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debouncer_vhdl

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-11-16
  • Size : 69kb
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  • Author :i*****
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Introduction - If you have any usage issues, please Google them yourself
RTL and testbench implementations for a switch debouncer with support for multiple switches, written in VHDL.
Packet file list
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debouncer_vhdl-master
.....................\bench
.....................\.....\debounce_atlys.ucf
.....................\.....\debounce_atlys_test.vhd
.....................\.....\debounce_atlys_test.wcfg
.....................\.....\debounce_atlys_top.par
.....................\.....\debounce_atlys_top.syr
.....................\.....\debounce_atlys_top.twr
.....................\.....\debounce_atlys_top.vhd
.....................\.....\debounce_atlys_top.xst
.....................\.....\debounce_atlys_top_bit.zip
.....................\.....\debounce_atlys_top_isim_beh1.wdb
.....................\.....\debounce_atlys_top_map.map
.....................\.....\debounce_atlys_top_map.mrp
.....................\.....\debounce_atlys_top_map.psr
.....................\.....\debounce_atlys_top_summary.html
.....................\.....\debounce_vhdl_bench.gise
.....................\.....\debounce_vhdl_bench.xise
.....................\.....\fuse.xmsgs
.....................\.....\fuseRelaunch.cmd
.....................\.....\grp_debouncer.vhd
.....................\.....\par_usage_statistics.html
.....................\.....\pepExtractor.prj
.....................\.....\readme.txt
.....................\.....\scope_photos.zip
.....................\license
.....................\.......\lgpl.txt
.....................\rtl
.....................\...\grp_debouncer.vhd
.....................\...\readme.txt
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