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shujujiance

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2015-11-30
  • Size : 474kb
  • Downloaded :0次
  • Author :陈****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Mealy-type single-process data monitoring. Achieve 100,101 data monitoring, enabling multiple portfolio monitoring, change transplantation convenient and simple.
Packet file list
(Preview for download)


db
..\prev_cmp_SCHK.map.qmsg
..\prev_cmp_SCHK.qmsg
..\prev_cmp_SCHK.sim.qmsg
..\SCHK.cbx.xml
..\SCHK.cmp.rdb
..\SCHK.cmp_merge.kpt
..\SCHK.db_info
..\SCHK.eco.cdb
..\SCHK.eds_overflow
..\SCHK.fnsim.cdb
..\SCHK.fnsim.hdb
..\SCHK.fnsim.qmsg
..\SCHK.hier_info
..\SCHK.hif
..\SCHK.lpc.html
..\SCHK.lpc.rdb
..\SCHK.lpc.txt
..\SCHK.map.bpm
..\SCHK.map.cdb
..\SCHK.map.ecobp
..\SCHK.map.hdb
..\SCHK.map.kpt
..\SCHK.map.logdb
..\SCHK.map.qmsg
..\SCHK.map_bb.cdb
..\SCHK.map_bb.hdb
..\SCHK.map_bb.logdb
..\SCHK.pre_map.cdb
..\SCHK.pre_map.hdb
..\SCHK.rtlv.hdb
..\SCHK.rtlv_sg.cdb
..\SCHK.rtlv_sg_swap.cdb
..\SCHK.sgdiff.cdb
..\SCHK.sgdiff.hdb
..\SCHK.sim.cvwf
..\SCHK.sim.hdb
..\SCHK.sim.qmsg
..\SCHK.sim.rdb
..\SCHK.simfam
..\SCHK.sim_ori.vwf
..\SCHK.sld_design_entry.sci
..\SCHK.sld_design_entry_dsc.sci
..\SCHK.smp_dump.txt
..\SCHK.syn_hier_info
..\SCHK.tis_db_list.ddb
..\SCHK.tmw_info
..\wed.wsf
incremental_db
..............\compiled_partitions
..............\...................\SCHK.root_partition.map.atm
..............\...................\SCHK.root_partition.map.dpi
..............\...................\SCHK.root_partition.map.hdbx
..............\...................\SCHK.root_partition.map.kpt
..............\README
SCHK.done
SCHK.flow.rpt
SCHK.map.rpt
SCHK.map.summary
SCHK.qpf
SCHK.qsf
SCHK.qws
SCHK.sim.rpt
SCHK.vhd
SCHK.vhd.bak
SCHK.vwf
数据检测 - 副本.jpg
数据检测.jpg
数据检测代码.jpg
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