The Cyclic Redundancy Check (CRC) is a checksum technique for testing data reliability and correctness. This application note shows how to implement Configurable CRC Modules with LocalLink interfaces. Users tailor the module features to suit the protocol or application implemented in their system. The user-specified options for each of the configurable features are input parameters to the VHDL code for the modules. The VHDL source files for the CRC modules are coded using generate statements. The modules have two LocalLink interfaces: an upstream interface (US) and a downstream interface (DS)

CRC校验参考设计2.pdf
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.......\faq
.......\readme
.......\src
.......\...\vhdl
.......\...\....\crc_components_pkg.vhd
.......\...\....\crc_functions_pkg.vhd
.......\...\....\crc_gen.vhd
.......\...\....\crc_valid_gen_rx.vhd
.......\...\....\data_ds_modules.vhd
.......\...\....\rem_ds_modules.vhd
.......\...\....\rxcrc.vhd
.......\...\....\rx_crc_example.vhd
.......\...\....\state_machine_rx.vhd
.......\...\....\state_machine_tx.vhd
.......\...\....\txcrc.vhd
.......\...\....\tx_crc_example.vhd
.......\synth
.......\.....\rxcrc.prj
.......\.....\rxcrc_xst.files
.......\.....\rxcrc_xst.scr
.......\.....\txcrc.prj
.......\.....\txcrc_xst.files
.......\.....\txcrc_xst.scr
.......\test
.......\....\func_sim
.......\....\........\stim
.......\....\........\....\stimfile_list
.......\....\........\....\tt_001.dat
.......\....\........\....\tt_002.dat
.......\....\........\....\tt_003.dat
.......\....\........\....\tt_004.dat
.......\....\........\....\tt_005.dat
.......\....\........\....\tt_006.dat
.......\....\........\....\tt_007.dat
.......\....\........\....\tt_008.dat
.......\....\........\....\tt_009.dat
.......\....\........\....\tt_010.dat
.......\....\........\vhdl_sim.do
.......\....\........\wave.do
.......\....\src
.......\....\...\vhdl
.......\....\...\....\crc_tb.vhd
.......\....\...\....\ll_stim.vhd

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